i82365.c

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/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 ********************************************************************
 *
 * Lots of code copied from:
 *
 * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
 * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
 * (C) 1999 David A. Hinds <[e-mail]>
 */

#include <common.h>

#ifdef CONFIG_I82365

#include <command.h>
#include <pci.h>
#include <pcmcia.h>
#include <asm/io.h>

#include <pcmcia/ss.h>
#include <pcmcia/i82365.h>
#include <pcmcia/yenta.h>
#ifdef CONFIG_CPC45
#include <pcmcia/cirrus.h>
#else
#include <pcmcia/ti113x.h>
#endif

static struct pci_device_id supported[] = {
#ifdef CONFIG_CPC45
	{PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
#else
	{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
#endif
	{0, 0}
};

#define CYCLE_TIME	120

#ifdef CONFIG_CPC45
extern int SPD67290Init (void);
#endif

#ifdef DEBUG
static void i82365_dump_regions (pci_dev_t dev);
#endif

typedef struct socket_info_t {
	pci_dev_t	dev;
	u_short		bcr;
	u_char		pci_lat, cb_lat, sub_bus, cache;
	u_int		cb_phys;

	socket_cap_t	cap;
	u_short		type;
	u_int		flags;
#ifdef CONFIG_CPC45
	cirrus_state_t	c_state;
#else
	ti113x_state_t	state;
#endif
} socket_info_t;

#ifdef CONFIG_CPC45
/* These definitions must match the pcic table! */
typedef enum pcic_id {
	IS_PD6710, IS_PD672X, IS_VT83C469
} pcic_id;

typedef struct pcic_t {
	char *name;
} pcic_t;

static pcic_t pcic[] = {
	{" Cirrus PD6710: "},
	{" Cirrus PD672x: "},
	{" VIA VT83C469: "},
};
#endif

static socket_info_t socket;
static socket_state_t state;
static struct pccard_mem_map mem;
static struct pccard_io_map io;

/*====================================================================*/

/* Some PCI shortcuts */

static int pci_readb (socket_info_t * s, int r, u_char * v)
{
	return pci_read_config_byte (s->dev, r, v);
}
static int pci_writeb (socket_info_t * s, int r, u_char v)
{
	return pci_write_config_byte (s->dev, r, v);
}
static int pci_readw (socket_info_t * s, int r, u_short * v)
{
	return pci_read_config_word (s->dev, r, v);
}
static int pci_writew (socket_info_t * s, int r, u_short v)
{
	return pci_write_config_word (s->dev, r, v);
}
#ifndef CONFIG_CPC45
static int pci_readl (socket_info_t * s, int r, u_int * v)
{
	return pci_read_config_dword (s->dev, r, v);
}
static int pci_writel (socket_info_t * s, int r, u_int v)
{
	return pci_write_config_dword (s->dev, r, v);
}
#endif	/* !CONFIG_CPC45 */

/*====================================================================*/

#ifdef CONFIG_CPC45

#define cb_readb(s)		readb((s)->cb_phys + 1)
#define cb_writeb(s, v)		writeb(v, (s)->cb_phys)
#define cb_writeb2(s, v)	writeb(v, (s)->cb_phys + 1)
#define cb_readl(s, r)		readl((s)->cb_phys + (r))
#define cb_writel(s, r, v)	writel(v, (s)->cb_phys + (r))


static u_char i365_get (socket_info_t * s, u_short reg)
{
	u_char val;

#ifdef CONFIG_PCMCIA_SLOT_A
	int slot = 0;
#else
	int slot = 1;
#endif

	val = I365_REG (slot, reg);

	cb_writeb (s, val);
	val = cb_readb (s);

	debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
	return val;
}

static void i365_set (socket_info_t * s, u_short reg, u_char data)
{
#ifdef CONFIG_PCMCIA_SLOT_A
	int slot = 0;
#else
	int slot = 1;
#endif

	u_char val = I365_REG (slot, reg);

	cb_writeb (s, val);
	cb_writeb2 (s, data);

	debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
}

#else	/* ! CONFIG_CPC45 */

#define cb_readb(s, r)		readb((s)->cb_phys + (r))
#define cb_readl(s, r)		readl((s)->cb_phys + (r))
#define cb_writeb(s, r, v)	writeb(v, (s)->cb_phys + (r))
#define cb_writel(s, r, v)	writel(v, (s)->cb_phys + (r))

static u_char i365_get (socket_info_t * s, u_short reg)
{
	return cb_readb (s, 0x0800 + reg);
}

static void i365_set (socket_info_t * s, u_short reg, u_char data)
{
	cb_writeb (s, 0x0800 + reg, data);
}
#endif	/* CONFIG_CPC45 */

static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
{
	i365_set (s, reg, i365_get (s, reg) | mask);
}

static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
{
	i365_set (s, reg, i365_get (s, reg) & ~mask);
}

#if 0	/* not used */
static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
{
	u_char d = i365_get (s, reg);

	i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
}

static u_short i365_get_pair (socket_info_t * s, u_short reg)
{
	return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
}
#endif	/* not used */

static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
{
	i365_set (s, reg, data & 0xff);
	i365_set (s, reg + 1, data >> 8);
}

#ifdef CONFIG_CPC45
/*======================================================================

    Code to save and restore global state information for Cirrus
    PD67xx controllers, and to set and report global configuration
    options.

======================================================================*/

#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))

static void cirrus_get_state (socket_info_t * s)
{
	int i;
	cirrus_state_t *p = &s->c_state;

	p->misc1 = i365_get (s, PD67_MISC_CTL_1);
	p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
	p->misc2 = i365_get (s, PD67_MISC_CTL_2);
	for (i = 0; i < 6; i++)
		p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);

}

static void cirrus_set_state (socket_info_t * s)
{
	int i;
	u_char misc;
	cirrus_state_t *p = &s->c_state;

	misc = i365_get (s, PD67_MISC_CTL_2);
	i365_set (s, PD67_MISC_CTL_2, p->misc2);
	if (misc & PD67_MC2_SUSPEND)
		udelay (50000);
	misc = i365_get (s, PD67_MISC_CTL_1);
	misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
	i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
	for (i = 0; i < 6; i++)
		i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
}

static u_int cirrus_set_opts (socket_info_t * s)
{
	cirrus_state_t *p = &s->c_state;
	u_int mask = 0xffff;

#if DEBUG
	char buf[200];

	memset (buf, 0, 200);
#endif

	if (has_ring == -1)
		has_ring = 1;
	flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
	flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
#if DEBUG
	if (p->misc2 & PD67_MC2_IRQ15_RI)
		strcat (buf, " [ring]");
	if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
		strcat (buf, " [dyn mode]");
	if (p->misc1 & PD67_MC1_INPACK_ENA)
		strcat (buf, " [inpack]");
#endif

	if (p->misc2 & PD67_MC2_IRQ15_RI)
		mask &= ~0x8000;
	if (has_led > 0) {
#if DEBUG
		strcat (buf, " [led]");
#endif
		mask &= ~0x1000;
	}
	if (has_dma > 0) {
#if DEBUG
		strcat (buf, " [dma]");
#endif
		mask &= ~0x0600;
		flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
#if DEBUG
		if (p->misc2 & PD67_MC2_FREQ_BYPASS)
			strcat (buf, " [freq bypass]");
#endif
	}

	if (setup_time >= 0)
		p->timer[0] = p->timer[3] = setup_time;
	if (cmd_time > 0) {
		p->timer[1] = cmd_time;
		p->timer[4] = cmd_time * 2 + 4;
	}
	if (p->timer[1] == 0) {
		p->timer[1] = 6;
		p->timer[4] = 16;
		if (p->timer[0] == 0)
			p->timer[0] = p->timer[3] = 1;
	}
	if (recov_time >= 0)
		p->timer[2] = p->timer[5] = recov_time;

	debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
		buf,
		p->timer[0], p->timer[1], p->timer[2],
		p->timer[3], p->timer[4], p->timer[5]);

	return mask;
}

#else	/* !CONFIG_CPC45 */

/*======================================================================

    Code to save and restore global state information for TI 1130 and
    TI 1131 controllers, and to set and report global configuration
    options.

======================================================================*/

static void ti113x_get_state (socket_info_t * s)
{
	ti113x_state_t *p = &s->state;

	pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
	pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
	pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
	pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
	pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
}

static void ti113x_set_state (socket_info_t * s)
{
	ti113x_state_t *p = &s->state;

	pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
	pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
	pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
	pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
	pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
	pci_writel (s, TI12XX_IRQMUX, p->irqmux);
	i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
	i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
}

static u_int ti113x_set_opts (socket_info_t * s)
{
	ti113x_state_t *p = &s->state;
	u_int mask = 0xffff;

	p->cardctl &= ~TI113X_CCR_ZVENABLE;
	p->cardctl |= TI113X_CCR_SPKROUTEN;

	return mask;
}
#endif	/* CONFIG_CPC45 */

/*======================================================================

    Routines to handle common CardBus options

======================================================================*/

/* Default settings for PCI command configuration register */
#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
		  PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)

static void cb_get_state (socket_info_t * s)
{
	pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
	pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
	pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
	pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
	pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
	pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
}

static void cb_set_state (socket_info_t * s)
{
#ifndef CONFIG_CPC45
	pci_writel (s, CB_LEGACY_MODE_BASE, 0);
	pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
#endif
	pci_writew (s, PCI_COMMAND, CMD_DFLT);
	pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
	pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
	pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
	pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
	pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
	pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
}

static void cb_set_opts (socket_info_t * s)
{
#ifndef CONFIG_CPC45
	if (s->cache == 0)
		s->cache = 8;
	if (s->pci_lat == 0)
		s->pci_lat = 0xa8;
	if (s->cb_lat == 0)
		s->cb_lat = 0xb0;
#endif
}

/*======================================================================

    Power control for Cardbus controllers: used both for 16-bit and
    Cardbus cards.

======================================================================*/

static int cb_set_power (socket_info_t * s, socket_state_t * state)
{
	u_int reg = 0;

#ifdef CONFIG_CPC45

	if ((state->Vcc == 0) && (state->Vpp == 0)) {
		u_char power, vcc, vpp;

		power = i365_get (s, I365_POWER);
		state->flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
		state->flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
		vcc = power & I365_VCC_MASK;
		vpp = power & I365_VPP1_MASK;
		state->Vcc = state->Vpp = 0;
		if (i365_get (s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) {
			if (power & I365_VCC_5V)
				state->Vcc = 33;
			if (vpp == I365_VPP1_5V)
				state->Vpp = 33;
		} else {
			if (power & I365_VCC_5V)
				state->Vcc = 50;
			if (vpp == I365_VPP1_5V)
				state->Vpp = 50;
		}
		if (power == I365_VPP1_12V)
			state->Vpp = 120;
		printf ("POWER Vcc:%d Vpp: %d\n", state->Vcc, state->Vpp);
	}

	reg = I365_PWR_NORESET;
	if (state->flags & SS_PWR_AUTO)
		reg |= I365_PWR_AUTO;
	if (state->flags & SS_OUTPUT_ENA)
		reg |= I365_PWR_OUT;
	if (state->Vpp != 0) {
		if (state->Vpp == 120) {
			reg |= I365_VPP1_12V;
			puts (" 12V card found: ");
		} else if (state->Vpp == state->Vcc) {
			reg |= I365_VPP1_5V;
			puts (" 5V card found: ");
		} else {
			puts (" power not found: ");
			return -1;
		}
	}
	if (state->Vcc != 0) {
		reg |= I365_VCC_5V;
		if (state->Vcc == 33) {
			puts (" 3.3V card found: ");
			i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
		} else if (state->Vcc == 50) {
			puts (" 5V card found: ");
			i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
		} else {
			puts (" power not found: ");
			return -1;
		}
	}
	if (reg != i365_get (s, I365_POWER))
		i365_set (s, I365_POWER, reg);

#else	/* ! CONFIG_CPC45 */

	/* restart card voltage detection if it seems appropriate */
	if ((state->Vcc == 0) && (state->Vpp == 0) &&
	   !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
		cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
	switch (state->Vcc) {