tigon3.h

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#define T3_CHIP_REV_5700_CX                 0x72
#define T3_CHIP_REV_5701_AX                 0x00

/* Metal revision. */
#define T3_METAL_REV(_ChipRevId)            ((_ChipRevId) & 0xff)
#define T3_METAL_REV_A0                     0x00
#define T3_METAL_REV_A1                     0x01
#define T3_METAL_REV_B0                     0x00
#define T3_METAL_REV_B1                     0x01
#define T3_METAL_REV_B2                     0x02

#define T3_PCI_REG_CLOCK_CTRL               0x74

#define T3_PCI_DISABLE_RX_CLOCK             BIT_10
#define T3_PCI_DISABLE_TX_CLOCK             BIT_11
#define T3_PCI_SELECT_ALTERNATE_CLOCK       BIT_12
#define T3_PCI_POWER_DOWN_PCI_PLL133        BIT_15
#define T3_PCI_44MHZ_CORE_CLOCK             BIT_18


#define T3_PCI_REG_ADDR_REG                 0x78
#define T3_PCI_REG_DATA_REG                 0x80

#define T3_PCI_MEM_WIN_ADDR_REG             0x7c
#define T3_PCI_MEM_WIN_DATA_REG             0x84

#define T3_PCI_PM_CAP_REG                   0x48

#define T3_PCI_PM_CAP_PME_D3COLD            BIT_31
#define T3_PCI_PM_CAP_PME_D3HOT             BIT_30

#define T3_PCI_PM_STATUS_CTRL_REG           0x4c

#define T3_PM_POWER_STATE_MASK              (BIT_0 | BIT_1)
#define T3_PM_POWER_STATE_D0                BIT_NONE
#define T3_PM_POWER_STATE_D1                BIT_0
#define T3_PM_POWER_STATE_D2                BIT_1
#define T3_PM_POWER_STATE_D3                (BIT_0 | BIT_1)

#define T3_PM_PME_ENABLE                    BIT_8
#define T3_PM_PME_ASSERTED                  BIT_15


/* PCI state register. */
#define T3_PCI_STATE_REG                    0x70

#define T3_PCI_STATE_FORCE_RESET            BIT_0
#define T3_PCI_STATE_INT_NOT_ACTIVE         BIT_1
#define T3_PCI_STATE_CONVENTIONAL_PCI_MODE  BIT_2
#define T3_PCI_STATE_BUS_SPEED_HIGH         BIT_3
#define T3_PCI_STATE_32BIT_PCI_BUS          BIT_4


/* Broadcom subsystem/subvendor IDs. */
#define T3_SVID_BROADCOM                            0x14e4

#define T3_SSID_BROADCOM_BCM95700A6                 0x1644
#define T3_SSID_BROADCOM_BCM95701A5                 0x0001
#define T3_SSID_BROADCOM_BCM95700T6                 0x0002  /* BCM8002 */
#define T3_SSID_BROADCOM_BCM95700A9                 0x0003  /* Agilent */
#define T3_SSID_BROADCOM_BCM95701T1                 0x0005
#define T3_SSID_BROADCOM_BCM95701T8                 0x0006
#define T3_SSID_BROADCOM_BCM95701A7                 0x0007  /* Agilent */
#define T3_SSID_BROADCOM_BCM95701A10                0x0008
#define T3_SSID_BROADCOM_BCM95701A12                0x8008
#define T3_SSID_BROADCOM_BCM95703Ax1                0x0009
#define T3_SSID_BROADCOM_BCM95703Ax2                0x8009

/* 3COM subsystem/subvendor IDs. */
#define T3_SVID_3COM                                0x10b7

#define T3_SSID_3COM_3C996T                         0x1000
#define T3_SSID_3COM_3C996BT                        0x1006
#define T3_SSID_3COM_3C996CT                        0x1002
#define T3_SSID_3COM_3C997T                         0x1003
#define T3_SSID_3COM_3C1000T                        0x1007
#define T3_SSID_3COM_3C940BR01                      0x1008

/* Fiber boards. */
#define T3_SSID_3COM_3C996SX                        0x1004
#define T3_SSID_3COM_3C997SX                        0x1005


/* Dell subsystem/subvendor IDs. */

#define T3_SVID_DELL                                0x1028

#define T3_SSID_DELL_VIPER                          0x00d1
#define T3_SSID_DELL_JAGUAR                         0x0106
#define T3_SSID_DELL_MERLOT                         0x0109
#define T3_SSID_DELL_SLIM_MERLOT                    0x010a

/* Compaq subsystem/subvendor IDs */

#define T3_SVID_COMPAQ                              0x0e11

#define T3_SSID_COMPAQ_BANSHEE                      0x007c
#define T3_SSID_COMPAQ_BANSHEE_2                    0x009a
#define T3_SSID_COMPAQ_CHANGELING                   0x007d
#define T3_SSID_COMPAQ_NC7780                       0x0085
#define T3_SSID_COMPAQ_NC7780_2                     0x0099


/******************************************************************************/
/* MII registers. */
/******************************************************************************/

/* Control register. */
#define PHY_CTRL_REG                                0x00

#define PHY_CTRL_SPEED_MASK                         (BIT_6 | BIT_13)
#define PHY_CTRL_SPEED_SELECT_10MBPS                BIT_NONE
#define PHY_CTRL_SPEED_SELECT_100MBPS               BIT_13
#define PHY_CTRL_SPEED_SELECT_1000MBPS              BIT_6
#define PHY_CTRL_COLLISION_TEST_ENABLE              BIT_7
#define PHY_CTRL_FULL_DUPLEX_MODE                   BIT_8
#define PHY_CTRL_RESTART_AUTO_NEG                   BIT_9
#define PHY_CTRL_ISOLATE_PHY                        BIT_10
#define PHY_CTRL_LOWER_POWER_MODE                   BIT_11
#define PHY_CTRL_AUTO_NEG_ENABLE                    BIT_12
#define PHY_CTRL_LOOPBACK_MODE                      BIT_14
#define PHY_CTRL_PHY_RESET                          BIT_15


/* Status register. */
#define PHY_STATUS_REG                              0x01

#define PHY_STATUS_LINK_PASS                        BIT_2
#define PHY_STATUS_AUTO_NEG_COMPLETE                BIT_5


/* Phy Id registers. */
#define PHY_ID1_REG                                 0x02
#define PHY_ID1_OUI_MASK                            0xffff

#define PHY_ID2_REG                                 0x03
#define PHY_ID2_REV_MASK                            0x000f
#define PHY_ID2_MODEL_MASK                          0x03f0
#define PHY_ID2_OUI_MASK                            0xfc00


/* Auto-negotiation advertisement register. */
#define PHY_AN_AD_REG                               0x04

#define PHY_AN_AD_ASYM_PAUSE                        BIT_11
#define PHY_AN_AD_PAUSE_CAPABLE                     BIT_10
#define PHY_AN_AD_10BASET_HALF                      BIT_5
#define PHY_AN_AD_10BASET_FULL                      BIT_6
#define PHY_AN_AD_100BASETX_HALF                    BIT_7
#define PHY_AN_AD_100BASETX_FULL                    BIT_8
#define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD            0x01


/* Auto-negotiation Link Partner Ability register. */
#define PHY_LINK_PARTNER_ABILITY_REG                0x05

#define PHY_LINK_PARTNER_ASYM_PAUSE                 BIT_11
#define PHY_LINK_PARTNER_PAUSE_CAPABLE              BIT_10


/* Auto-negotiation expansion register. */
#define PHY_AN_EXPANSION_REG                        0x06


/******************************************************************************/
/* BCM5400 and BCM5401 phy info. */
/******************************************************************************/

#define PHY_DEVICE_ID           1

/* OUI: bit 31-10;   Model#: bit 9-4;   Rev# bit 3-0. */
#define PHY_UNKNOWN_PHY                             0x00000000
#define PHY_BCM5400_PHY_ID                          0x60008040
#define PHY_BCM5401_PHY_ID                          0x60008050
#define PHY_BCM5411_PHY_ID                          0x60008070
#define PHY_BCM5701_PHY_ID                          0x60008110
#define PHY_BCM5703_PHY_ID                          0x60008160
#define PHY_BCM5704_PHY_ID                          0x60008190
#define PHY_BCM8002_PHY_ID                          0x60010140

#define PHY_BCM5401_B0_REV                          0x1
#define PHY_BCM5401_B2_REV                          0x3
#define PHY_BCM5401_C0_REV                          0x6

#define PHY_ID_OUI_MASK                             0xfffffc00
#define PHY_ID_MODEL_MASK                           0x000003f0
#define PHY_ID_REV_MASK                             0x0000000f
#define PHY_ID_MASK                                 (PHY_ID_OUI_MASK |      \
						    PHY_ID_MODEL_MASK)


#define UNKNOWN_PHY_ID(x)   ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \
			    (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \
			    (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \
			    (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \
			    (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \
			    (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \
			    (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID))


/* 1000Base-T control register. */
#define BCM540X_1000BASET_CTRL_REG                  0x09

#define BCM540X_AN_AD_1000BASET_HALF                BIT_8
#define BCM540X_AN_AD_1000BASET_FULL                BIT_9
#define BCM540X_CONFIG_AS_MASTER                    BIT_11
#define BCM540X_ENABLE_CONFIG_AS_MASTER             BIT_12


/* Extended control register. */
#define BCM540X_EXT_CTRL_REG                        0x10

#define BCM540X_EXT_CTRL_LINK3_LED_MODE             BIT_1
#define BCM540X_EXT_CTRL_TBI                        BIT_15

/* PHY extended status register. */
#define BCM540X_EXT_STATUS_REG                      0x11

#define BCM540X_EXT_STATUS_LINK_PASS                BIT_8


/* DSP Coefficient Read/Write Port. */
#define BCM540X_DSP_RW_PORT                         0x15


/* DSP Coeficient Address Register. */
#define BCM540X_DSP_ADDRESS_REG                     0x17

#define BCM540X_DSP_TAP_NUMBER_MASK                 0x00
#define BCM540X_DSP_AGC_A                           0x00
#define BCM540X_DSP_AGC_B                           0x01
#define BCM540X_DSP_MSE_PAIR_STATUS                 0x02
#define BCM540X_DSP_SOFT_DECISION                   0x03
#define BCM540X_DSP_PHASE_REG                       0x04
#define BCM540X_DSP_SKEW                            0x05
#define BCM540X_DSP_POWER_SAVER_UPPER_BOUND         0x06
#define BCM540X_DSP_POWER_SAVER_LOWER_BOUND         0x07
#define BCM540X_DSP_LAST_ECHO                       0x08
#define BCM540X_DSP_FREQUENCY                       0x09
#define BCM540X_DSP_PLL_BANDWIDTH                   0x0a
#define BCM540X_DSP_PLL_PHASE_OFFSET                0x0b

#define BCM540X_DSP_FILTER_DCOFFSET                 (BIT_10 | BIT_11)
#define BCM540X_DSP_FILTER_FEXT3                    (BIT_8 | BIT_9 | BIT_11)
#define BCM540X_DSP_FILTER_FEXT2                    (BIT_9 | BIT_11)
#define BCM540X_DSP_FILTER_FEXT1                    (BIT_8 | BIT_11)
#define BCM540X_DSP_FILTER_FEXT0                    BIT_11
#define BCM540X_DSP_FILTER_NEXT3                    (BIT_8 | BIT_9 | BIT_10)
#define BCM540X_DSP_FILTER_NEXT2                    (BIT_9 | BIT_10)
#define BCM540X_DSP_FILTER_NEXT1                    (BIT_8 | BIT_10)
#define BCM540X_DSP_FILTER_NEXT0                    BIT_10
#define BCM540X_DSP_FILTER_ECHO                     (BIT_8 | BIT_9)
#define BCM540X_DSP_FILTER_DFE                      BIT_9
#define BCM540X_DSP_FILTER_FFE                      BIT_8

#define BCM540X_DSP_CONTROL_ALL_FILTERS             BIT_12

#define BCM540X_DSP_SEL_CH_0                        BIT_NONE
#define BCM540X_DSP_SEL_CH_1                        BIT_13
#define BCM540X_DSP_SEL_CH_2                        BIT_14
#define BCM540X_DSP_SEL_CH_3                        (BIT_13 | BIT_14)

#define BCM540X_CONTROL_ALL_CHANNELS                BIT_15


/* Auxilliary Control Register (Shadow Register) */
#define BCM5401_AUX_CTRL                            0x18

#define BCM5401_SHADOW_SEL_MASK                     0x7
#define BCM5401_SHADOW_SEL_NORMAL                   0x00
#define BCM5401_SHADOW_SEL_10BASET                  0x01
#define BCM5401_SHADOW_SEL_POWER_CONTROL            0x02
#define BCM5401_SHADOW_SEL_IP_PHONE                 0x03
#define BCM5401_SHADOW_SEL_MISC_TEST1               0x04
#define BCM5401_SHADOW_SEL_MISC_TEST2               0x05
#define BCM5401_SHADOW_SEL_IP_PHONE_SEED            0x06


/* Shadow register selector == '000' */
#define BCM5401_SHDW_NORMAL_DIAG_MODE               BIT_3
#define BCM5401_SHDW_NORMAL_DISABLE_MBP             BIT_4
#define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR         BIT_5
#define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF         BIT_6
#define BCM5401_SHDW_NORMAL_DISABLE_PRF             BIT_7
#define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL       BIT_NONE
#define BCM5401_SHDW_NORMAL_RX_SLICING_4D           BIT_8
#define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D      BIT_9
#define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D      (BIT_8 | BIT_9)
#define BCM5401_SHDW_NORMAL_TX_6DB_CODING           BIT_10
#define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK     BIT_11
#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS       BIT_NONE
#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS       BIT_12
#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS       BIT_13
#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS       (BIT_12 | BIT_13)
#define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH       BIT_14
#define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK       BIT_15


/* Auxilliary status summary. */
#define BCM540X_AUX_STATUS_REG                      0x19

#define BCM540X_AUX_LINK_PASS                       BIT_2
#define BCM540X_AUX_SPEED_MASK                      (BIT_8 | BIT_9 | BIT_10)
#define BCM540X_AUX_10BASET_HD                      BIT_8
#define BCM540X_AUX_10BASET_FD                      BIT_9
#define BCM540X_AUX_100BASETX_HD                    (BIT_8 | BIT_9)
#define BCM540X_AUX_100BASET4                       BIT_10
#define BCM540X_AUX_100BASETX_FD                    (BIT_8 | BIT_10)
#define BCM540X_AUX_100BASET_HD                     (BIT_9 | BIT_10)
#define BCM540X_AUX_100BASET_FD                     (BIT_8 | BIT_9 | BIT_10)


/* Interrupt status. */
#define BCM540X_INT_STATUS_REG                      0x1a

#define BCM540X_INT_LINK_CHANGE                     BIT_1
#define BCM540X_INT_SPEED_CHANGE                    BIT_2
#define BCM540X_INT_DUPLEX_CHANGE                   BIT_3
#define BCM540X_INT_AUTO_NEG_PAGE_RX                BIT_10


/* Interrupt mask register. */
#define BCM540X_INT_MASK_REG                        0x1b


/******************************************************************************/
/* Register definitions. */
/******************************************************************************/

typedef volatile LM_UINT8 T3_8BIT_REGISTER, *PT3_8BIT_REGISTER;
typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER;
typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER;

typedef struct {
    /* Big endian format. */
    T3_32BIT_REGISTER High;
    T3_32BIT_REGISTER Low;
} T3_64BIT_REGISTER, *PT3_64BIT_REGISTER;

typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR;

#define T3_NUM_OF_DMA_DESC    256
#define T3_NUM_OF_MBUF        768

typedef struct
{
  T3_64BIT_REGISTER host_addr;
  T3_32BIT_REGISTER nic_mbuf;
  T3_16BIT_REGISTER len;
  T3_16BIT_REGISTER cqid_sqid;
  T3_32BIT_REGISTER flags;
  T3_32BIT_REGISTER opaque1;
  T3_32BIT_REGISTER opaque2;
  T3_32BIT_REGISTER opaque3;
}T3_DMA_DESC, *PT3_DMA_DESC;


/******************************************************************************/
/* Ring control block. */
/******************************************************************************/

typedef struct {
    T3_64BIT_REGISTER HostRingAddr;

    union {
	struct {
#ifdef BIG_ENDIAN_HOST
	    T3_16BIT_REGISTER MaxLen;
	    T3_16BIT_REGISTER Flags;