tigon3.h

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/******************************************************************************/
/*                                                                            */
/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom         */
/* Corporation.                                                               */
/* All rights reserved.                                                       */
/*                                                                            */
/* This program is free software; you can redistribute it and/or modify       */
/* it under the terms of the GNU General Public License as published by       */
/* the Free Software Foundation, located in the file LICENSE.                 */
/*                                                                            */
/* History:                                                                   */
/*                                                                            */
/******************************************************************************/

#ifndef TIGON3_H
#define TIGON3_H

#include "bcm570x_lm.h"
#if INCLUDE_TBI_SUPPORT
#include "bcm570x_autoneg.h"
#endif


/* io defines */
#if !defined(BIG_ENDIAN_HOST)
#define readl(addr) \
	      (LONGSWAP((*(volatile unsigned int *)(addr))))
#define writel(b,addr) \
	      ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b)))
#else
#if 0 /* !defined(PPC603) */
#define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr)))
#define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b))
#else
#if 1
#define readl(addr) (*(volatile unsigned int*)(addr))
#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
#else
extern int sprintf(char* buf, const char* f, ...);
static __inline unsigned int readl(void* addr){
    char buf[128];
    unsigned int tmp = (*(volatile unsigned int*)(addr));
    sprintf(buf,"%s:%s: read 0x%x from 0x%x\n",__FILE__,__LINE__,tmp,addr,0,0);
    sysSerialPrintString(buf);
    return tmp;
}
static __inline void writel(unsigned int b, unsigned int addr){
    char buf[128];
    ((*(volatile unsigned int *) (addr)) = (b));
    sprintf(buf,"%s:%s: write 0x%x to 0x%x\n",__FILE__,__LINE__,b,addr,0,0);
    sysSerialPrintString(buf);
}
#endif
#endif /* PPC603 */
#endif


/******************************************************************************/
/* Constants. */
/******************************************************************************/

/* Maxim number of packet descriptors used for sending packets. */
#define MAX_TX_PACKET_DESC_COUNT            600
#define DEFAULT_TX_PACKET_DESC_COUNT        2

/* Maximum number of packet descriptors used for receiving packets. */
#if T3_JUMBO_RCB_ENTRY_COUNT
#define MAX_RX_PACKET_DESC_COUNT                                            \
    (T3_STD_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT)
#else
#define MAX_RX_PACKET_DESC_COUNT            800
#endif
#define DEFAULT_RX_PACKET_DESC_COUNT        2

/* Threshhold for double copying small tx packets.  0 will disable double */
/* copying of small Tx packets. */
#define DEFAULT_TX_COPY_BUFFER_SIZE         0
#define MIN_TX_COPY_BUFFER_SIZE             64
#define MAX_TX_COPY_BUFFER_SIZE             512

/* Cache line. */
#define COMMON_CACHE_LINE_SIZE              0x20
#define COMMON_CACHE_LINE_MASK              (COMMON_CACHE_LINE_SIZE-1)

/* Maximum number of fragment we can handle. */
#ifndef MAX_FRAGMENT_COUNT
#define MAX_FRAGMENT_COUNT                  32
#endif

/* B0 bug. */
#define BCM5700_BX_MIN_FRAG_SIZE            10
#define BCM5700_BX_MIN_FRAG_BUF_SIZE        16  /* nice aligned size. */
#define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK   (BCM5700_BX_MIN_FRAG_BUF_SIZE-1)
#define BCM5700_BX_TX_COPY_BUF_SIZE         (BCM5700_BX_MIN_FRAG_BUF_SIZE * \
					    MAX_FRAGMENT_COUNT)

/* MAGIC number. */
/* #define T3_MAGIC_NUM                        'KevT' */
#define T3_FIRMWARE_MAILBOX                0x0b50
#define T3_MAGIC_NUM                       0x4B657654
#define T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b

#define T3_NIC_DATA_SIG_ADDR               0x0b54
#define T3_NIC_DATA_SIG                    0x4b657654

#define T3_NIC_DATA_NIC_CFG_ADDR           0x0b58
#define T3_NIC_CFG_LED_MODE_UNKNOWN        BIT_NONE
#define T3_NIC_CFG_LED_MODE_TRIPLE_SPEED   BIT_2
#define T3_NIC_CFG_LED_MODE_LINK_SPEED     BIT_3
#define T3_NIC_CFG_LED_MODE_OPEN_DRAIN     BIT_2
#define T3_NIC_CFG_LED_MODE_OUTPUT         BIT_3
#define T3_NIC_CFG_LED_MODE_MASK           (BIT_2 | BIT_3)
#define T3_NIC_CFG_PHY_TYPE_UNKNOWN         BIT_NONE
#define T3_NIC_CFG_PHY_TYPE_COPPER          BIT_4
#define T3_NIC_CFG_PHY_TYPE_FIBER           BIT_5
#define T3_NIC_CFG_PHY_TYPE_MASK            (BIT_4 | BIT_5)
#define T3_NIC_CFG_ENABLE_WOL               BIT_6
#define T3_NIC_CFG_ENABLE_ASF               BIT_7
#define T3_NIC_EEPROM_WP                    BIT_8

#define T3_NIC_DATA_PHY_ID_ADDR            0x0b74
#define T3_NIC_PHY_ID1_MASK                0xffff0000
#define T3_NIC_PHY_ID2_MASK                0x0000ffff

#define T3_CMD_MAILBOX                      0x0b78
#define T3_CMD_NICDRV_ALIVE                 0x01
#define T3_CMD_NICDRV_PAUSE_FW              0x02
#define T3_CMD_NICDRV_IPV4ADDR_CHANGE       0x03
#define T3_CMD_NICDRV_IPV6ADDR_CHANGE       0x04
#define T3_CMD_5703A0_FIX_DMAFW_DMAR        0x05
#define T3_CMD_5703A0_FIX_DMAFW_DMAW        0x06

#define T3_CMD_LENGTH_MAILBOX               0x0b7c
#define T3_CMD_DATA_MAILBOX                 0x0b80

#define T3_ASF_FW_STATUS_MAILBOX            0x0c00

#define T3_DRV_STATE_MAILBOX                0x0c04
#define T3_DRV_STATE_START                  0x01
#define T3_DRV_STATE_UNLOAD                 0x02
#define T3_DRV_STATE_WOL                    0x03
#define T3_DRV_STATE_SUSPEND                0x04

#define T3_FW_RESET_TYPE_MAILBOX            0x0c08

#define T3_MAC_ADDR_HIGH_MAILBOX            0x0c14
#define T3_MAC_ADDR_LOW_MAILBOX             0x0c18

/******************************************************************************/
/* Hardware constants. */
/******************************************************************************/

/* Number of entries in the send ring:  must be 512. */
#define T3_SEND_RCB_ENTRY_COUNT             512
#define T3_SEND_RCB_ENTRY_COUNT_MASK        (T3_SEND_RCB_ENTRY_COUNT-1)

/* Number of send RCBs.  May be 1-16 but for now, only support one. */
#define T3_MAX_SEND_RCB_COUNT               16

/* Number of entries in the Standard Receive RCB.  Must be 512 entries. */
#define T3_STD_RCV_RCB_ENTRY_COUNT          512
#define T3_STD_RCV_RCB_ENTRY_COUNT_MASK     (T3_STD_RCV_RCB_ENTRY_COUNT-1)
#define DEFAULT_STD_RCV_DESC_COUNT          200    /* Must be < 512. */
#define MAX_STD_RCV_BUFFER_SIZE             0x600

/* Number of entries in the Mini Receive RCB.  This value can either be */
/* 0, 1024.  Currently Mini Receive RCB is disabled. */
#ifndef T3_MINI_RCV_RCB_ENTRY_COUNT
#define T3_MINI_RCV_RCB_ENTRY_COUNT         0
#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */
#define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK    (T3_MINI_RCV_RCB_ENTRY_COUNT-1)
#define MAX_MINI_RCV_BUFFER_SIZE            512
#define DEFAULT_MINI_RCV_BUFFER_SIZE        64
#define DEFAULT_MINI_RCV_DESC_COUNT         100    /* Must be < 1024. */

/* Number of entries in the Jumbo Receive RCB.  This value must 256 or 0. */
/* Currently, Jumbo Receive RCB is disabled. */
#ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT
#define T3_JUMBO_RCV_RCB_ENTRY_COUNT        0
#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
#define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK   (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1)

#define MAX_JUMBO_RCV_BUFFER_SIZE           (10 * 1024) /* > 1514 */
#define DEFAULT_JUMBO_RCV_BUFFER_SIZE       (4 * 1024) /* > 1514 */
#define DEFAULT_JUMBO_RCV_DESC_COUNT        128     /* Must be < 256. */

#define MAX_JUMBO_TX_BUFFER_SIZE            (8 * 1024) /* > 1514 */
#define DEFAULT_JUMBO_TX_BUFFER_SIZE        (4 * 1024) /* > 1514 */

/* Number of receive return RCBs.  Maybe 1-16 but for now, only support one. */
#define T3_MAX_RCV_RETURN_RCB_COUNT         16

/* Number of entries in a Receive Return ring.  This value is either 1024 */
/* or 2048. */
#ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT
#define T3_RCV_RETURN_RCB_ENTRY_COUNT       1024
#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */
#define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK  (T3_RCV_RETURN_RCB_ENTRY_COUNT-1)


/* Default coalescing parameters. */
#define DEFAULT_RX_COALESCING_TICKS         100
#define MAX_RX_COALESCING_TICKS             500
#define DEFAULT_TX_COALESCING_TICKS         400
#define MAX_TX_COALESCING_TICKS             500
#define DEFAULT_RX_MAX_COALESCED_FRAMES     10
#define MAX_RX_MAX_COALESCED_FRAMES         100
#define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES    5
#define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES    42
#define ADAPTIVE_LO_RX_COALESCING_TICKS         50
#define ADAPTIVE_HI_RX_COALESCING_TICKS         300
#define ADAPTIVE_LO_PKT_THRESH              30000
#define ADAPTIVE_HI_PKT_THRESH              74000
#define DEFAULT_TX_MAX_COALESCED_FRAMES     40
#define ADAPTIVE_LO_TX_MAX_COALESCED_FRAMES    25
#define ADAPTIVE_HI_TX_MAX_COALESCED_FRAMES    75
#define MAX_TX_MAX_COALESCED_FRAMES         100

#define DEFAULT_RX_COALESCING_TICKS_DURING_INT          25
#define DEFAULT_TX_COALESCING_TICKS_DURING_INT          25
#define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT      5
#define DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT      5

#define BAD_DEFAULT_VALUE                               0xffffffff

#define DEFAULT_STATS_COALESCING_TICKS      1000000
#define MAX_STATS_COALESCING_TICKS          3600000000U


/* Receive BD Replenish thresholds. */
#define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD      4
#define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD    4

#define SPLIT_MODE_DISABLE                          0
#define SPLIT_MODE_ENABLE                           1

#define SPLIT_MODE_5704_MAX_REQ                     3

/* Maximum physical fragment size. */
#define MAX_FRAGMENT_SIZE                   (64 * 1024)


/* Standard view. */
#define T3_STD_VIEW_SIZE                    (64 * 1024)
#define T3_FLAT_VIEW_SIZE                   (32 * 1024 * 1024)


/* Buffer descriptor base address on the NIC's memory. */

#define T3_NIC_SND_BUFFER_DESC_ADDR         0x4000
#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR     0x6000
#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR   0x7000

#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR_EXT_MEM     0xc000
#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR_EXT_MEM   0xd000
#define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM    0xe000

#define T3_NIC_SND_BUFFER_DESC_SIZE         (T3_SEND_RCB_ENTRY_COUNT * \
					    sizeof(T3_SND_BD) / 4)

#define T3_NIC_STD_RCV_BUFFER_DESC_SIZE     (T3_STD_RCV_RCB_ENTRY_COUNT * \
					    sizeof(T3_RCV_BD) / 4)

#define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE   (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \
					    sizeof(T3_EXT_RCV_BD) / 4)


/* MBUF pool. */
#define T3_NIC_MBUF_POOL_ADDR               0x8000
/* #define T3_NIC_MBUF_POOL_SIZE               0x18000 */
#define T3_NIC_MBUF_POOL_SIZE96             0x18000
#define T3_NIC_MBUF_POOL_SIZE64             0x10000


#define T3_NIC_MBUF_POOL_ADDR_EXT_MEM       0x20000

/* DMA descriptor pool */
#define T3_NIC_DMA_DESC_POOL_ADDR           0x2000
#define T3_NIC_DMA_DESC_POOL_SIZE           0x2000      /* 8KB. */

#define T3_DEF_DMA_MBUF_LOW_WMARK           0x40
#define T3_DEF_RX_MAC_MBUF_LOW_WMARK        0x20
#define T3_DEF_MBUF_HIGH_WMARK              0x60

#define T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO     304
#define T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO  152
#define T3_DEF_MBUF_HIGH_WMARK_JUMBO        380

#define T3_DEF_DMA_DESC_LOW_WMARK           5
#define T3_DEF_DMA_DESC_HIGH_WMARK          10

/* Maximum size of giant TCP packet can be sent */
#define T3_TCP_SEG_MAX_OFFLOAD_SIZE         64*1000
#define T3_TCP_SEG_MIN_NUM_SEG              20

#define T3_RX_CPU_ID    0x1
#define T3_TX_CPU_ID    0x2
#define T3_RX_CPU_SPAD_ADDR  0x30000
#define T3_RX_CPU_SPAD_SIZE  0x4000
#define T3_TX_CPU_SPAD_ADDR  0x34000
#define T3_TX_CPU_SPAD_SIZE  0x4000

typedef struct T3_DIR_ENTRY
{
  PLM_UINT8 Buffer;
  LM_UINT32 Offset;
  LM_UINT32 Length;
} T3_DIR_ENTRY,*PT3_DIR_ENTRY;

typedef struct T3_FWIMG_INFO
{
  LM_UINT32 StartAddress;
  T3_DIR_ENTRY Text;
  T3_DIR_ENTRY ROnlyData;
  T3_DIR_ENTRY Data;
  T3_DIR_ENTRY Sbss;
  T3_DIR_ENTRY Bss;
} T3_FWIMG_INFO, *PT3_FWIMG_INFO;


/******************************************************************************/
/* Tigon3 PCI Registers. */
/******************************************************************************/
#define T3_PCI_ID_BCM5700                   0x164414e4
#define T3_PCI_ID_BCM5701                   0x164514e4
#define T3_PCI_ID_BCM5702                   0x164614e4
#define T3_PCI_ID_BCM5702x                  0x16A614e4
#define T3_PCI_ID_BCM5703                   0x164714e4
#define T3_PCI_ID_BCM5703x                  0x16A714e4
#define T3_PCI_ID_BCM5702FE                 0x164D14e4
#define T3_PCI_ID_BCM5704                   0x164814e4

#define T3_PCI_VENDOR_ID                    (T3_PCI_ID & 0xffff)
#define T3_PCI_DEVICE_ID                    (T3_PCI_ID >> 16)

#define T3_PCI_MISC_HOST_CTRL_REG           0x68

/* The most significant 16bit of register 0x68. */
/* ChipId:4, ChipRev:4, MetalRev:8 */
#define T3_CHIP_ID_5700_A0                  0x7000
#define T3_CHIP_ID_5700_A1                  0x7001
#define T3_CHIP_ID_5700_B0                  0x7100
#define T3_CHIP_ID_5700_B1                  0x7101
#define T3_CHIP_ID_5700_C0                  0x7200

#define T3_CHIP_ID_5701_A0                  0x0000
#define T3_CHIP_ID_5701_B0                  0x0100
#define T3_CHIP_ID_5701_B2                  0x0102
#define T3_CHIP_ID_5701_B5                  0x0105

#define T3_CHIP_ID_5703_A0                  0x1000
#define T3_CHIP_ID_5703_A1                  0x1001
#define T3_CHIP_ID_5703_A2                  0x1002

#define T3_CHIP_ID_5704_A0                  0x2000

/* Chip Id. */
#define T3_ASIC_REV(_ChipRevId)             ((_ChipRevId) >> 12)
#define T3_ASIC_REV_5700                    0x07
#define T3_ASIC_REV_5701                    0x00
#define T3_ASIC_REV_5703                    0x01
#define T3_ASIC_REV_5704                    0x02


/* Chip id and revision. */
#define T3_CHIP_REV(_ChipRevId)             ((_ChipRevId) >> 8)
#define T3_CHIP_REV_5700_AX                 0x70
#define T3_CHIP_REV_5700_BX                 0x71