tigon3.c

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    /* Create receive packet descriptors from the memory block and add them */
    /* to the RxPacketFreeQ.  Create the Standard packet descriptors. */
    for(j = 0; j < pDevice->RxStdDescCnt; j++)
    {
	/* Receive producer ring. */
	pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;

	/* Receive buffer size. */
	pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;

	/* Add the descriptor to RxPacketFreeQ. */
	QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);

	/* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
	/* is the total size of the packet descriptor including the */
	/* os-specific extensions in the UM_PACKET structure. */
	pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
    } /* for */

#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
    /* Create the Jumbo packet descriptors. */
    for(j = 0; j < pDevice->RxJumboDescCnt; j++)
    {
	/* Receive producer ring. */
	pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;

	/* Receive buffer size. */
	pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;

	/* Add the descriptor to RxPacketFreeQ. */
	QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);

	/* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
	/* is the total size of the packet descriptor including the */
	/* os-specific extensions in the UM_PACKET structure. */
	pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
    } /* for */
#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */

    /* Initialize the rest of the packet descriptors. */
    Status = MM_InitializeUmPackets(pDevice);
    if(Status != LM_STATUS_SUCCESS)
    {
	return Status;
    } /* if */

    /* Default receive mask. */
    pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
	LM_ACCEPT_UNICAST;

    /* Make sure we are in the first 32k memory window or NicSendBd. */
    REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);

    /* Initialize the hardware. */
    Status = LM_ResetAdapter(pDevice);
    if(Status != LM_STATUS_SUCCESS)
    {
	return Status;
    }

    /* We are done with initialization. */
    pDevice->InitDone = TRUE;

    return LM_STATUS_SUCCESS;
} /* LM_InitializeAdapter */


/******************************************************************************/
/* Description:                                                               */
/*    This function Enables/Disables a given block.                          */
/*                                                                            */
/* Return:                                                                    */
/*    LM_STATUS_SUCCESS                                                       */
/******************************************************************************/
LM_STATUS
LM_CntrlBlock(
PLM_DEVICE_BLOCK pDevice,
LM_UINT32 mask,LM_UINT32 cntrl)
{
    LM_UINT32 j,i,data;
    LM_UINT32 MaxWaitCnt;

    MaxWaitCnt = 2;
    j = 0;

    for(i = 0 ; i < 32; i++)
    {
	if(!(mask & (1 << i)))
	    continue;

	switch (1 << i)
	{
	    case T3_BLOCK_DMA_RD:
		data = REG_RD(pDevice, DmaRead.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~DMA_READ_MODE_ENABLE;
		    REG_WR(pDevice, DmaRead.Mode, data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, DmaRead.Mode, data | DMA_READ_MODE_ENABLE);
		break;

	    case T3_BLOCK_DMA_COMP:
		data = REG_RD(pDevice,DmaComp.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~DMA_COMP_MODE_ENABLE;
		    REG_WR(pDevice, DmaComp.Mode, data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, DmaComp.Mode, data | DMA_COMP_MODE_ENABLE);
		break;

	    case T3_BLOCK_RX_BD_INITIATOR:
		data = REG_RD(pDevice, RcvBdIn.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~RCV_BD_IN_MODE_ENABLE;
		    REG_WR(pDevice, RcvBdIn.Mode,data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, RcvBdIn.Mode,data | RCV_BD_IN_MODE_ENABLE);
		break;

	    case T3_BLOCK_RX_BD_COMP:
		data = REG_RD(pDevice, RcvBdComp.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~RCV_BD_COMP_MODE_ENABLE;
		    REG_WR(pDevice, RcvBdComp.Mode,data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, RcvBdComp.Mode,data | RCV_BD_COMP_MODE_ENABLE);
		break;

	    case T3_BLOCK_DMA_WR:
		data = REG_RD(pDevice, DmaWrite.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~DMA_WRITE_MODE_ENABLE;
		    REG_WR(pDevice, DmaWrite.Mode,data);

		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, DmaWrite.Mode,data | DMA_WRITE_MODE_ENABLE);
		break;

	    case T3_BLOCK_MSI_HANDLER:
		data = REG_RD(pDevice, Msi.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~MSI_MODE_ENABLE;
		    REG_WR(pDevice, Msi.Mode, data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, Msi.Mode) & MSI_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, Msi.Mode, data |MSI_MODE_ENABLE);
		break;

	    case T3_BLOCK_RX_LIST_PLMT:
		data = REG_RD(pDevice, RcvListPlmt.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~RCV_LIST_PLMT_MODE_ENABLE;
		    REG_WR(pDevice, RcvListPlmt.Mode,data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, RcvListPlmt.Mode,data | RCV_LIST_PLMT_MODE_ENABLE);
		break;

	    case T3_BLOCK_RX_LIST_SELECTOR:
		data = REG_RD(pDevice, RcvListSel.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~RCV_LIST_SEL_MODE_ENABLE;
		    REG_WR(pDevice, RcvListSel.Mode,data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, RcvListSel.Mode,data |RCV_LIST_SEL_MODE_ENABLE);
		break;

	    case T3_BLOCK_RX_DATA_INITIATOR:
		data = REG_RD(pDevice, RcvDataBdIn.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
		    REG_WR(pDevice, RcvDataBdIn.Mode,data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, RcvDataBdIn.Mode, data | RCV_DATA_BD_IN_MODE_ENABLE);
		break;

	    case T3_BLOCK_RX_DATA_COMP:
		data = REG_RD(pDevice, RcvDataComp.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~RCV_DATA_COMP_MODE_ENABLE;
		    REG_WR(pDevice, RcvDataComp.Mode,data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, RcvDataComp.Mode,data | RCV_DATA_COMP_MODE_ENABLE);
		break;

	    case T3_BLOCK_HOST_COALESING:
		data = REG_RD(pDevice, HostCoalesce.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~HOST_COALESCE_ENABLE;
		    REG_WR(pDevice, HostCoalesce.Mode, data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, HostCoalesce.Mode, data | HOST_COALESCE_ENABLE);
		break;

	    case T3_BLOCK_MAC_RX_ENGINE:
		if(cntrl == LM_DISABLE)
		{
		    pDevice->RxMode &= ~RX_MODE_ENABLE;
		    REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE))
			{
			    break;
			}
			MM_Wait(10);
		    }
		}
		else
		{
		    pDevice->RxMode |= RX_MODE_ENABLE;
		    REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
		}
		break;

	    case T3_BLOCK_MBUF_CLUSTER_FREE:
		data = REG_RD(pDevice, MbufClusterFree.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
		    REG_WR(pDevice, MbufClusterFree.Mode,data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, MbufClusterFree.Mode, data | MBUF_CLUSTER_FREE_MODE_ENABLE);
		break;

	    case T3_BLOCK_SEND_BD_INITIATOR:
		data = REG_RD(pDevice, SndBdIn.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~SND_BD_IN_MODE_ENABLE;
		    REG_WR(pDevice, SndBdIn.Mode, data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, SndBdIn.Mode, data  | SND_BD_IN_MODE_ENABLE);
		break;

	    case T3_BLOCK_SEND_BD_COMP:
		data = REG_RD(pDevice, SndBdComp.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~SND_BD_COMP_MODE_ENABLE;
		    REG_WR(pDevice, SndBdComp.Mode, data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, SndBdComp.Mode, data | SND_BD_COMP_MODE_ENABLE);
		break;

	    case T3_BLOCK_SEND_BD_SELECTOR:
		data = REG_RD(pDevice, SndBdSel.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~SND_BD_SEL_MODE_ENABLE;
		    REG_WR(pDevice, SndBdSel.Mode, data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, SndBdSel.Mode, data | SND_BD_SEL_MODE_ENABLE);
		break;

	    case T3_BLOCK_SEND_DATA_INITIATOR:
		data = REG_RD(pDevice, SndDataIn.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~T3_SND_DATA_IN_MODE_ENABLE;
		    REG_WR(pDevice, SndDataIn.Mode,data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, SndDataIn.Mode,data | T3_SND_DATA_IN_MODE_ENABLE);
		break;

	    case T3_BLOCK_SEND_DATA_COMP:
		data = REG_RD(pDevice, SndDataComp.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~SND_DATA_COMP_MODE_ENABLE;
		    REG_WR(pDevice, SndDataComp.Mode, data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, SndDataComp.Mode,data | SND_DATA_COMP_MODE_ENABLE);
		break;

	    case T3_BLOCK_MAC_TX_ENGINE:
		if(cntrl == LM_DISABLE)
		{
		    pDevice->TxMode &= ~TX_MODE_ENABLE;
		    REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		{
		    pDevice->TxMode |= TX_MODE_ENABLE;
		    REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
		}
		break;

	    case T3_BLOCK_MEM_ARBITOR:
		data = REG_RD(pDevice, MemArbiter.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~T3_MEM_ARBITER_MODE_ENABLE;
		    REG_WR(pDevice, MemArbiter.Mode, data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE))
			    break;
			MM_Wait(10);
		    }
		}
		else
		    REG_WR(pDevice, MemArbiter.Mode,data|T3_MEM_ARBITER_MODE_ENABLE);
		break;

	    case T3_BLOCK_MBUF_MANAGER:
		data = REG_RD(pDevice, BufMgr.Mode);
		if (cntrl == LM_DISABLE)
		{
		    data &= ~BUFMGR_MODE_ENABLE;
		    REG_WR(pDevice, BufMgr.Mode,data);
		    for(j = 0; j < MaxWaitCnt; j++)
		    {
			if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR