tigon3.c

F:worksip2440a board可启动u-boot-like.tar.gz F:worksip2440a board可启动u-boot-like.tar.gz

	    HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
    }

    /* Set the status block size. */
    if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
	T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX)
    {
	pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
    }

    /* Check the DURING_INT coalescing ticks parameters. */
    if(pDevice->UseTaggedStatus)
    {
	if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
	{
	    pDevice->RxCoalescingTicksDuringInt =
		DEFAULT_RX_COALESCING_TICKS_DURING_INT;
	}

	if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
	{
	    pDevice->TxCoalescingTicksDuringInt =
		DEFAULT_TX_COALESCING_TICKS_DURING_INT;
	}

	if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
	{
	    pDevice->RxMaxCoalescedFramesDuringInt =
		DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
	}

	if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
	{
	    pDevice->TxMaxCoalescedFramesDuringInt =
		DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
	}
    }
    else
    {
	if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
	{
	    pDevice->RxCoalescingTicksDuringInt = 0;
	}

	if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
	{
	    pDevice->TxCoalescingTicksDuringInt = 0;
	}

	if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
	{
	    pDevice->RxMaxCoalescedFramesDuringInt = 0;
	}

	if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
	{
	    pDevice->TxMaxCoalescedFramesDuringInt = 0;
	}
    }

#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
    if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */))
    {
	pDevice->RxJumboDescCnt = 0;
	if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC)
	{
	    pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
	}
    }
    else
    {
	pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ +
	    COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK;

	if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE)
	{
	    pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE;
	    pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */;
	}
	pDevice->TxMtu = pDevice->RxMtu;

    }
#else
    pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */

    pDevice->RxPacketDescCnt =
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
	pDevice->RxJumboDescCnt +
#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
	pDevice->RxStdDescCnt;

    if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC)
    {
	pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
    }

    if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE)
    {
	pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
    }

    /* Configure the proper ways to get link change interrupt. */
    if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO)
    {
	if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
	{
	    pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
	}
	else
	{
	    pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
	}
    }
    else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
    {
	/* Auto-polling does not work on 5700_AX and 5700_BX. */
	if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
	{
	    pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
	}
    }

    /* Determine the method to get link change status. */
    if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO)
    {
	/* The link status bit in the status block does not work on 5700_AX */
	/* and 5700_BX chips. */
	if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
	{
	    pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
	}
	else
	{
	    pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
	}
    }

    if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
	T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
    {
	pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
    }

    /* Configure PHY led mode. */
    if(pDevice->LedMode == LED_MODE_AUTO)
    {
	if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
	    T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
	{
	    if(pDevice->SubsystemVendorId == T3_SVID_DELL)
	    {
		pDevice->LedMode = LED_MODE_LINK10;
	    }
	    else
	    {
		pDevice->LedMode = LED_MODE_THREE_LINK;

		if(EeSigFound && EePhyLedMode != LED_MODE_AUTO)
		{
		    pDevice->LedMode = EePhyLedMode;
		}
	    }

	    /* bug? 5701 in LINK10 mode does not seem to work when */
	    /* PhyIntMode is LINK_READY. */
	    if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
#if INCLUDE_TBI_SUPPORT
		pDevice->EnableTbi == FALSE &&
#endif
		pDevice->LedMode == LED_MODE_LINK10)
	    {
		pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
		pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
	    }

	    if(pDevice->EnableTbi)
	    {
		pDevice->LedMode = LED_MODE_THREE_LINK;
	    }
	}
	else
	{
	    if(EeSigFound && EePhyLedMode != LED_MODE_AUTO)
	    {
		pDevice->LedMode = EePhyLedMode;
	    }
	    else
	    {
		pDevice->LedMode = LED_MODE_OPEN_DRAIN;
	    }
	}
    }

    /* Enable OneDmaAtOnce. */
    if(pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE)
    {
	pDevice->OneDmaAtOnce = FALSE;
    }

    if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
	pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
	pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
	pDevice->ChipRevId == T3_CHIP_ID_5701_B2)
    {
	pDevice->WolSpeed = WOL_SPEED_10MB;
    }
    else
    {
	pDevice->WolSpeed = WOL_SPEED_100MB;
    }

    /* Offloadings. */
    pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;

    /* Turn off task offloading on Ax. */
    if(pDevice->ChipRevId == T3_CHIP_ID_5700_B0)
    {
	pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
	    LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
    }
    pDevice->PciState = REG_RD(pDevice, PciCfg.PciState);
    LM_ReadVPD(pDevice);
    LM_ReadBootCodeVersion(pDevice);
    LM_GetBusSpeed(pDevice);

    return LM_STATUS_SUCCESS;
} /* LM_GetAdapterInfo */

STATIC PLM_ADAPTER_INFO
LM_GetAdapterInfoBySsid(
    LM_UINT16 Svid,
    LM_UINT16 Ssid)
{
    static LM_ADAPTER_INFO AdapterArr[] =
    {
	{ T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0},
	{ T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0},
	{ T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1},
	{ T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 },
	{ T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0},
	{ T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0},
	{ T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
	{ T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0},
	{ T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0},
	{ T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5701_PHY_ID, 0},
	{ T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5701_PHY_ID, 0},

	{ T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 },
	{ T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 },
	{ T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 },
	{ T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 },
	{ T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 },

	{ T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 },
	{ T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 },
	{ T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 },
	{ T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 },

	{ T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 },
	{ T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 },
	{ T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 },
	{ T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 },
	{ T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 },

    };
    LM_UINT32 j;

    for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++)
    {
	if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid)
	{
	    return &AdapterArr[j];
	}
    }

    return NULL;
}


/******************************************************************************/
/* Description:                                                               */
/*    This routine sets up receive/transmit buffer descriptions queues.       */
/*                                                                            */
/* Return:                                                                    */
/*    LM_STATUS_SUCCESS                                                       */
/******************************************************************************/
LM_STATUS
LM_InitializeAdapter(
PLM_DEVICE_BLOCK pDevice)
{
    LM_PHYSICAL_ADDRESS MemPhy;
    PLM_UINT8 pMemVirt;
    PLM_PACKET pPacket;
    LM_STATUS Status;
    LM_UINT32 Size;
    LM_UINT32 j;

    /* Set power state to D0. */
    LM_SetPowerState(pDevice, LM_POWER_STATE_D0);

    /* Intialize the queues. */
    QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container,
	MAX_RX_PACKET_DESC_COUNT);
    QQ_InitQueue(&pDevice->RxPacketFreeQ.Container,
	MAX_RX_PACKET_DESC_COUNT);

    QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT);
    QQ_InitQueue(&pDevice->TxPacketActiveQ.Container,MAX_TX_PACKET_DESC_COUNT);
    QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT);

    /* Allocate shared memory for: status block, the buffers for receive */
    /* rings -- standard, mini, jumbo, and return rings. */
    Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) +
	T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
	T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
	T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);

    /* Memory for host based Send BD. */
    if(pDevice->NicSendBd == FALSE)
    {
	Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
    }

    /* Allocate the memory block. */
    Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE);
    if(Status != LM_STATUS_SUCCESS)
    {
	return Status;
    }

    /* Program DMA Read/Write */
    if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS)
    {
	pDevice->DmaReadWriteCtrl = 0x763f000f;
    }
    else
    {
	if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
	{
	    pDevice->DmaReadWriteCtrl = 0x761f0000;
	}
	else
	{
	    pDevice->DmaReadWriteCtrl = 0x761b000f;
	}
	if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
	    pDevice->ChipRevId == T3_CHIP_ID_5703_A2)
	{
	    pDevice->OneDmaAtOnce = TRUE;
	}
    }
    if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
    {
	pDevice->DmaReadWriteCtrl &= 0xfffffff0;
    }

    if(pDevice->OneDmaAtOnce)
    {
	pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
    }
    REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);

    if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS)
    {
	return LM_STATUS_FAILURE;
    }

    /* Status block. */
    pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
    pDevice->StatusBlkPhy = MemPhy;
    pMemVirt += T3_STATUS_BLOCK_SIZE;
    LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE);

    /* Statistics block. */
    pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
    pDevice->StatsBlkPhy = MemPhy;
    pMemVirt += sizeof(T3_STATS_BLOCK);
    LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK));

    /* Receive standard BD buffer. */
    pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
    pDevice->RxStdBdPhy = MemPhy;

    pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
    LM_INC_PHYSICAL_ADDRESS(&MemPhy,
	T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));

#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
    /* Receive jumbo BD buffer. */
    pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
    pDevice->RxJumboBdPhy = MemPhy;

    pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
    LM_INC_PHYSICAL_ADDRESS(&MemPhy,
	T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */

    /* Receive return BD buffer. */
    pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
    pDevice->RcvRetBdPhy = MemPhy;

    pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
    LM_INC_PHYSICAL_ADDRESS(&MemPhy,
	T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));

    /* Set up Send BD. */
    if(pDevice->NicSendBd == FALSE)
    {
	pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
	pDevice->SendBdPhy = MemPhy;

	pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
	LM_INC_PHYSICAL_ADDRESS(&MemPhy,
	    sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT);
    }
    else
    {
	pDevice->pSendBdVirt = (PT3_SND_BD)
	    pDevice->pMemView->uIntMem.First32k.BufferDesc;
	pDevice->SendBdPhy.High = 0;
	pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
    }

    /* Allocate memory for packet descriptors. */
    Size = (pDevice->RxPacketDescCnt +
	pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
    Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket);
    if(Status != LM_STATUS_SUCCESS)
    {
	return Status;
    }
    pDevice->pPacketDescBase = (PLM_VOID) pPacket;

    /* Create transmit packet descriptors from the memory block and add them */
    /* to the TxPacketFreeQ for each send ring. */
    for(j = 0; j < pDevice->TxPacketDescCnt; j++)
    {
	/* Ring index. */
	pPacket->Flags = 0;

	/* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
	QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);

	/* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
	/* is the total size of the packet descriptor including the */
	/* os-specific extensions in the UM_PACKET structure. */
	pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
    } /* for(j.. */