tigon3.c

F:worksip2440a board可启动u-boot-like.tar.gz F:worksip2440a board可启动u-boot-like.tar.gz

	if(Value32 & NVRAM_CMD_DONE)
	{
	    Status = LM_STATUS_SUCCESS;
	}
	else
	{
	    Status = LM_STATUS_FAILURE;
	}
    }

    return Status;
} /* LM_NvramRead */


STATIC void
LM_ReadVPD(PLM_DEVICE_BLOCK pDevice)
{
    LM_UINT32 Vpd_arr[256/4];
    LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0];
    LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
    LM_UINT32 Value32;
    unsigned int j;

    /* Read PN from VPD */
    for (j = 0; j < 256; j += 4, Vpd_dptr++ )
    {
	if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) {
	    printf("BCM570x: LM_ReadVPD: VPD read failed"
		   " (no EEPROM onboard)\n");
	    return;
	}
	*Vpd_dptr = cpu_to_le32(Value32);
    }
    for (j = 0; j < 256; )
    {
	unsigned int Vpd_r_len;
	unsigned int Vpd_r_end;

	if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91))
	{
	    j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
	}
	else if (Vpd[j] == 0x90)
	{
	    Vpd_r_len =  Vpd[j + 1] + (Vpd[j + 2] << 8);
	    j += 3;
	    Vpd_r_end = Vpd_r_len + j;
	    while (j < Vpd_r_end)
	    {
		if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N'))
		{
		    unsigned int len = Vpd[j + 2];

		    if (len <= 24)
		    {
			memcpy(pDevice->PartNo, &Vpd[j + 3], len);
		    }
		    break;
		}
		else
		{
		    if (Vpd[j + 2] == 0)
		    {
			break;
		    }
		    j = j + Vpd[j + 2];
		}
	    }
	    break;
	}
	else {
	    break;
	}
    }
}

STATIC void
LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice)
{
    LM_UINT32 Value32, offset, ver_offset;
    int i;

    if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
	return;
    if (Value32 != 0xaa559966)
	return;
    if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
	return;

    offset = ((offset & 0xff) << 24)| ((offset & 0xff00) << 8)|
	((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff);
    if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
	return;
    if ((Value32 == 0x0300000e) &&
	(LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) &&
	(Value32 == 0)) {

	if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS)
	    return;
	ver_offset = ((ver_offset & 0xff0000) >> 8) |
	    ((ver_offset >> 24) & 0xff);
	for (i = 0; i < 16; i += 4) {
	    if (LM_NvramRead(pDevice, offset + ver_offset + i, &Value32) !=
		LM_STATUS_SUCCESS)
	    {
		return;
	    }
	    *((LM_UINT32 *) &pDevice->BootCodeVer[i]) = cpu_to_le32(Value32);
	}
    }
    else {
	char c;

	if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
	    return;

	i = 0;
	c = ((Value32 & 0xff0000) >> 16);

	if (c < 10) {
	    pDevice->BootCodeVer[i++] = c + '0';
	}
	else {
	    pDevice->BootCodeVer[i++] = (c / 10) + '0';
	    pDevice->BootCodeVer[i++] = (c % 10) + '0';
	}
	pDevice->BootCodeVer[i++] = '.';
	c = (Value32 & 0xff000000) >> 24;
	if (c < 10) {
	    pDevice->BootCodeVer[i++] = c + '0';
	}
	else {
	    pDevice->BootCodeVer[i++] = (c / 10) + '0';
	    pDevice->BootCodeVer[i++] = (c % 10) + '0';
	}
	pDevice->BootCodeVer[i] = 0;
    }
}

STATIC void
LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice)
{
    LM_UINT32 PciState = pDevice->PciState;
    LM_UINT32 ClockCtrl;
    char *SpeedStr = "";

    if (PciState & T3_PCI_STATE_32BIT_PCI_BUS)
    {
	strcpy(pDevice->BusSpeedStr, "32-bit ");
    }
    else
    {
	strcpy(pDevice->BusSpeedStr, "64-bit ");
    }
    if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)
    {
	strcat(pDevice->BusSpeedStr, "PCI ");
	if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED)
	{
	    SpeedStr = "66MHz";
	}
	else
	{
	    SpeedStr = "33MHz";
	}
    }
    else
    {
	strcat(pDevice->BusSpeedStr, "PCIX ");
	if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)
	{
	    SpeedStr = "133MHz";
	}
	else
	{
	    ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f;
	    switch (ClockCtrl)
	    {
	    case 0:
		SpeedStr = "33MHz";
		break;

	    case 2:
		SpeedStr = "50MHz";
		break;

	    case 4:
		SpeedStr = "66MHz";
		break;

	    case 6:
		SpeedStr = "100MHz";
		break;

	    case 7:
		SpeedStr = "133MHz";
		break;
	    }
	}
    }
    strcat(pDevice->BusSpeedStr, SpeedStr);
}

/******************************************************************************/
/* Description:                                                               */
/*    This routine initializes default parameters and reads the PCI           */
/*    configurations.                                                         */
/*                                                                            */
/* Return:                                                                    */
/*    LM_STATUS_SUCCESS                                                       */
/******************************************************************************/
LM_STATUS
LM_GetAdapterInfo(
PLM_DEVICE_BLOCK pDevice)
{
    PLM_ADAPTER_INFO pAdapterInfo;
    LM_UINT32 Value32;
    LM_STATUS Status;
    LM_UINT32 j;
    LM_UINT32 EeSigFound;
    LM_UINT32 EePhyTypeSerdes = 0;
    LM_UINT32 EePhyLedMode = 0;
    LM_UINT32 EePhyId = 0;

    /* Get Device Id and Vendor Id */
    Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32);
    if(Status != LM_STATUS_SUCCESS)
    {
	return Status;
    }
    pDevice->PciVendorId = (LM_UINT16) Value32;
    pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);

    /* If we are not getting the write adapter, exit. */
    if((Value32 != T3_PCI_ID_BCM5700) &&
       (Value32 != T3_PCI_ID_BCM5701) &&
       (Value32 != T3_PCI_ID_BCM5702) &&
       (Value32 != T3_PCI_ID_BCM5702x) &&
       (Value32 != T3_PCI_ID_BCM5702FE) &&
       (Value32 != T3_PCI_ID_BCM5703) &&
       (Value32 != T3_PCI_ID_BCM5703x) &&
       (Value32 != T3_PCI_ID_BCM5704))
    {
	return LM_STATUS_FAILURE;
    }

    Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32);
    if(Status != LM_STATUS_SUCCESS)
    {
	return Status;
    }
    pDevice->PciRevId = (LM_UINT8) Value32;

    /* Get IRQ. */
    Status = MM_ReadConfig32(pDevice, PCI_INT_LINE_REG, &Value32);
    if(Status != LM_STATUS_SUCCESS)
    {
	return Status;
    }
    pDevice->Irq = (LM_UINT8) Value32;

    /* Get interrupt pin. */
    pDevice->IntPin = (LM_UINT8) (Value32 >> 8);

    /* Get chip revision id. */
    Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
    pDevice->ChipRevId = Value32 >> 16;

    /* Get subsystem vendor. */
    Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
    if(Status != LM_STATUS_SUCCESS)
    {
	return Status;
    }
    pDevice->SubsystemVendorId = (LM_UINT16) Value32;

    /* Get PCI subsystem id. */
    pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);

    /* Get the cache line size. */
    MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
    pDevice->CacheLineSize = (LM_UINT8) Value32;
    pDevice->SavedCacheLineReg = Value32;

    if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
	pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
	pDevice->ChipRevId != T3_CHIP_ID_5704_A0)
    {
	pDevice->UndiFix = FALSE;
    }
#if !PCIX_TARGET_WORKAROUND
    pDevice->UndiFix = FALSE;
#endif
    /* Map the memory base to system address space. */
    if (!pDevice->UndiFix)
    {
	Status = MM_MapMemBase(pDevice);
	if(Status != LM_STATUS_SUCCESS)
	{
	    return Status;
	}
	/* Initialize the memory view pointer. */
	pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
    }

#if PCIX_TARGET_WORKAROUND
    /* store whether we are in PCI are PCI-X mode */
    pDevice->EnablePciXFix = FALSE;

    MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
    if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)
    {
	/* Enable PCI-X workaround only if we are running on 5700 BX. */
	if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
	{
	    pDevice->EnablePciXFix = TRUE;
	}
    }
    if (pDevice->UndiFix)
    {
	pDevice->EnablePciXFix = TRUE;
    }
#endif
    /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
    /* management register may be clobbered which may cause the */
    /* BCM5700 to go into D3 state.  While in this state, we will */
    /* not have memory mapped register access.  As a workaround, we */
    /* need to restore the device to D0 state. */
    MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
    Value32 |= T3_PM_PME_ASSERTED;
    Value32 &= ~T3_PM_POWER_STATE_MASK;
    Value32 |= T3_PM_POWER_STATE_D0;
    MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);

    /* read the current PCI command word */
    MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);

    /* Make sure bus-mastering is enabled. */
    Value32 |= PCI_BUSMASTER_ENABLE;

#if PCIX_TARGET_WORKAROUND
    /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
	are enabled */
    if (pDevice->EnablePciXFix == TRUE) {
	Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
		    PCI_PARITY_ERROR_ENABLE);
    }
    if (pDevice->UndiFix)
    {
	Value32 &= ~PCI_MEM_SPACE_ENABLE;
    }

#endif

    if(pDevice->EnableMWI)
    {
	Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
    }
    else {
	Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
    }

    /* Error out if mem-mapping is NOT enabled for PCI systems */
    if (!(Value32 | PCI_MEM_SPACE_ENABLE))
    {
	return LM_STATUS_FAILURE;
    }

    /* save the value we are going to write into the PCI command word */
    pDevice->PciCommandStatusWords = Value32;

    Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32);
    if(Status != LM_STATUS_SUCCESS)
    {
	return Status;
    }

    /* Set power state to D0. */
    LM_SetPowerState(pDevice, LM_POWER_STATE_D0);

#ifdef BIG_ENDIAN_PCI
    pDevice->MiscHostCtrl =
	MISC_HOST_CTRL_MASK_PCI_INT |
	MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
	MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
	MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
#else /* No CPU Swap modes for PCI IO */

    /* Setup the mode registers. */
    pDevice->MiscHostCtrl =
	MISC_HOST_CTRL_MASK_PCI_INT |
	MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
#ifdef BIG_ENDIAN_HOST
	MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
#endif /* BIG_ENDIAN_HOST */
	MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
	MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
#endif /* !BIG_ENDIAN_PCI */

    /* write to PCI misc host ctr first in order to enable indirect accesses */
    MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);

    REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl);

#ifdef BIG_ENDIAN_PCI
    Value32 = GRC_MODE_WORD_SWAP_DATA|
	      GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
#else
/* No CPU Swap modes for PCI IO */
#ifdef BIG_ENDIAN_HOST
    Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
	      GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
#else
    Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
#endif
#endif /* !BIG_ENDIAN_PCI */

    REG_WR(pDevice, Grc.Mode, Value32);

    if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
    {
	REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
	    GRC_MISC_LOCAL_CTRL_GPIO_OE1);
    }
    MM_Wait(40);

    /* Enable indirect memory access */
    REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);

    if (REG_RD(pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK)
    {
	REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK |
		T3_PCI_SELECT_ALTERNATE_CLOCK);
	REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_SELECT_ALTERNATE_CLOCK);
	MM_Wait(40);  /* required delay is 27usec */
    }
    REG_WR(pDevice, PciCfg.ClockCtrl, 0);
    REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);

#if PCIX_TARGET_WORKAROUND
    MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
    if ((pDevice->EnablePciXFix == FALSE) &&
	((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0))
    {
	if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
	    pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
	    pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
	    pDevice->ChipRevId == T3_CHIP_ID_5701_B5)
	{
	    __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x300]));
	    __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301]));