ct69000.c

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/*
 * (C) Copyright 2002
 * Denis Peter, MPL AG Switzerland
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * ported from ctfb.c (linux kernel) for the U-Boot
 *
 */


#include <common.h>

#ifdef CONFIG_VIDEO

#include <pci.h>
#include <video_fb.h>
#include "videomodes.h"

#ifdef CONFIG_VIDEO_CT69000

/* debug */
#undef VGA_DEBUG
#undef VGA_DUMP_REG
#ifdef VGA_DEBUG
#define	PRINTF(fmt,args...)	printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif

/* Macros */
#ifndef min
#define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b )
#endif
#ifndef max
#define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b )
#endif
#ifdef minmax
#error "term minmax already used."
#endif
#define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) )
#define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) )

/* CT Register Offsets */
#define CT_AR_O			0x3c0	/* Index and Data write port of the attribute Registers */
#define CT_GR_O			0x3ce	/* Index port of the Graphic Controller Registers */
#define CT_SR_O			0x3c4	/* Index port of the Sequencer Controller */
#define CT_CR_O			0x3d4	/* Index port of the CRT Controller */
#define CT_XR_O			0x3d6	/* Extended Register index */
#define CT_MSR_W_O		0x3c2	/* Misc. Output Register (write only) */
#define CT_LUT_MASK_O		0x3c6	/* Color Palette Mask */
#define CT_LUT_START_O		0x3c8	/* Color Palette Write Mode Index */
#define CT_LUT_RGB_O		0x3c9	/* Color Palette Data Port */
#define CT_STATUS_REG0_O	0x3c2	/* Status Register 0 (read only) */
#define CT_STATUS_REG1_O	0x3da	/* Input Status Register 1 (read only) */

#define CT_FP_O			0x3d0	/* Index port of the Flat panel Registers */
#define CT_MR_O			0x3d2	/* Index Port of the Multimedia Extension */

/* defines for the memory mapped registers */
#define BR00_o		0x400000	/* Source and Destination Span Register */
#define BR01_o		0x400004	/* Pattern/Source Expansion Background Color & Transparency Key Register */
#define BR02_o		0x400008	/* Pattern/Source Expansion Foreground Color Register */
#define BR03_o		0x40000C	/* Monochrome Source Control Register */
#define BR04_o		0x400010	/* BitBLT Control Register */
#define BR05_o		0x400014	/* Pattern Address Registe */
#define BR06_o		0x400018	/* Source Address Register */
#define BR07_o		0x40001C	/* Destination Address Register */
#define BR08_o		0x400020	/* Destination Width & Height Register */
#define BR09_o		0x400024	/* Source Expansion Background Color & Transparency Key Register */
#define BR0A_o		0x400028	/* Source Expansion Foreground Color Register */

#define CURSOR_SIZE	0x1000	/* in KByte for HW Cursor */
#define PATTERN_ADR	(pGD->dprBase + CURSOR_SIZE)	/* pattern Memory after Cursor Memory */
#define PATTERN_SIZE	8*8*4	/* 4 Bytes per Pixel 8 x 8 Pixel */
#define ACCELMEMORY	(CURSOR_SIZE + PATTERN_SIZE)	/* reserved Memory for BITBlt and hw cursor */

/* Some Mode definitions */
#define FB_SYNC_HOR_HIGH_ACT	1	/* horizontal sync high active  */
#define FB_SYNC_VERT_HIGH_ACT	2	/* vertical sync high active    */
#define FB_SYNC_EXT		4	/* external sync                */
#define FB_SYNC_COMP_HIGH_ACT	8	/* composite sync high active   */
#define FB_SYNC_BROADCAST	16	/* broadcast video timings      */
					/* vtotal = 144d/288n/576i => PAL  */
					/* vtotal = 121d/242n/484i => NTSC */
#define FB_SYNC_ON_GREEN	32	/* sync on green */

#define FB_VMODE_NONINTERLACED  0	/* non interlaced */
#define FB_VMODE_INTERLACED	1	/* interlaced   */
#define FB_VMODE_DOUBLE		2	/* double scan */
#define FB_VMODE_MASK		255

#define FB_VMODE_YWRAP		256	/* ywrap instead of panning     */
#define FB_VMODE_SMOOTH_XPAN	512	/* smooth xpan possible (internally used) */
#define FB_VMODE_CONUPDATE	512	/* don't update x/yoffset       */

#define text			0
#define fntwidth		8

/* table for VGA Initialization  */
typedef struct {
	const unsigned char reg;
	const unsigned char val;
} CT_CFG_TABLE;

/* this table provides some basic initialisations such as Memory Clock etc */
static CT_CFG_TABLE xreg[] = {
	{0x09, 0x01},		/* CRT Controller Extensions Enable */
	{0x0A, 0x02},		/* Frame Buffer Mapping */
	{0x0B, 0x01},		/* PCI Write Burst support */
	{0x20, 0x00},		/* BitBLT Configuration */
	{0x40, 0x03},		/* Memory Access Control */
	{0x60, 0x00},		/* Video Pin Control */
	{0x61, 0x00},		/* DPMS Synch control */
	{0x62, 0x00},		/* GPIO Pin Control */
	{0x63, 0xBD},		/* GPIO Pin Data */
	{0x67, 0x00},		/* Pin Tri-State */
	{0x80, 0x80},		/* Pixel Pipeline Config 0 register */
	{0xA0, 0x00},		/* Cursor 1 Control Reg */
	{0xA1, 0x00},		/* Cursor 1 Vertical Extension Reg */
	{0xA2, 0x00},		/* Cursor 1 Base Address Low */
	{0xA3, 0x00},		/* Cursor 1 Base Address High */
	{0xA4, 0x00},		/* Cursor 1 X-Position Low */
	{0xA5, 0x00},		/* Cursor 1 X-Position High */
	{0xA6, 0x00},		/* Cursor 1 Y-Position Low */
	{0xA7, 0x00},		/* Cursor 1 Y-Position High */
	{0xA8, 0x00},		/* Cursor 2 Control Reg */
	{0xA9, 0x00},		/* Cursor 2 Vertical Extension Reg */
	{0xAA, 0x00},		/* Cursor 2 Base Address Low */
	{0xAB, 0x00},		/* Cursor 2 Base Address High */
	{0xAC, 0x00},		/* Cursor 2 X-Position Low */
	{0xAD, 0x00},		/* Cursor 2 X-Position High */
	{0xAE, 0x00},		/* Cursor 2 Y-Position Low */
	{0xAF, 0x00},		/* Cursor 2 Y-Position High */
	{0xC0, 0x7D},		/* Dot Clock 0 VCO M-Divisor */
	{0xC1, 0x07},		/* Dot Clock 0 VCO N-Divisor */
	{0xC3, 0x34},		/* Dot Clock 0 Divisor select */
	{0xC4, 0x55},		/* Dot Clock 1 VCO M-Divisor */
	{0xC5, 0x09},		/* Dot Clock 1 VCO N-Divisor */
	{0xC7, 0x24},		/* Dot Clock 1 Divisor select */
	{0xC8, 0x7D},		/* Dot Clock 2 VCO M-Divisor */
	{0xC9, 0x07},		/* Dot Clock 2 VCO N-Divisor */
	{0xCB, 0x34},		/* Dot Clock 2 Divisor select */
	{0xCC, 0x38},		/* Memory Clock 0 VCO M-Divisor */
	{0xCD, 0x03},		/* Memory Clock 0 VCO N-Divisor */
	{0xCE, 0x90},		/* Memory Clock 0 Divisor select */
	{0xCF, 0x06},		/* Clock Config */
	{0xD0, 0x0F},		/* Power Down */
	{0xD1, 0x01},		/* Power Down BitBLT */
	{0xFF, 0xFF}		/* end of table */
};
/* Clock Config:
 * =============
 *
 * PD Registers:
 * -------------
 * Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor.
 * They are encoded as follows:
 *
 * +---+--------------+
 * | 2 | Loop Divisor |
 * +---+--------------+
 * | 1 | 1            |
 * +---+--------------+
 * | 0 | 4            |
 * +---+--------------+
 * Note: The Memory Clock does not have a Loop Divisor.
 * +---+---+---+--------------+
 * | 6 | 5 | 4 | Post Divisor |
 * +---+---+---+--------------+
 * | 0 | 0 | 0 | 1            |
 * +---+---+---+--------------+
 * | 0 | 0 | 1 | 2            |
 * +---+---+---+--------------+
 * | 0 | 1 | 0 | 4            |
 * +---+---+---+--------------+
 * | 0 | 1 | 1 | 8            |
 * +---+---+---+--------------+
 * | 1 | 0 | 0 | 16           |
 * +---+---+---+--------------+
 * | 1 | 0 | 1 | 32           |
 * +---+---+---+--------------+
 * | 1 | 1 | X | reserved     |
 * +---+---+---+--------------+
 *
 * All other bits are reserved in these registers.
 *
 * Clock VCO M Registers:
 * ----------------------
 * These Registers contain the M Value -2.
 *
 * Clock VCO N Registers:
 * ----------------------
 * These Registers contain the N Value -2.
 *
 * Formulas:
 * ---------
 * Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz
 * Fout = Fvco / Post Divisor
 *
 * Dot Clk0 (default 25MHz):
 * -------------------------
 * Fvco = 14.318 * 127 / 9 = 202.045MHz
 * Fout = 202.045MHz / 8 = 25.25MHz
 * Post Divisor = 8
 * Loop Divisor = 1
 * XRC0 = (M - 2) = 125 = 0x7D
 * XRC1 = (N - 2) = 7   = 0x07
 * XRC3 =                 0x34
 *
 * Dot Clk1 (default 28MHz):
 * -------------------------
 * Fvco = 14.318 * 87 / 11 = 113.24MHz
 * Fout = 113.24MHz / 4 = 28.31MHz
 * Post Divisor = 4
 * Loop Divisor = 1
 * XRC4 = (M - 2) = 85 = 0x55
 * XRC5 = (N - 2) = 9  = 0x09
 * XRC7 =                0x24
 *
 * Dot Clk2 (variable for extended modes set to 25MHz):
 * ----------------------------------------------------
 * Fvco = 14.318 * 127 / 9 = 202.045MHz
 * Fout = 202.045MHz / 8 = 25.25MHz
 * Post Divisor = 8
 * Loop Divisor = 1
 * XRC8 = (M - 2) = 125 = 0x7D
 * XRC9 = (N - 2) = 7   = 0x07
 * XRCB =                 0x34
 *
 * Memory Clk for most modes >50MHz:
 * ----------------------------------
 * Fvco = 14.318 * 58 / 5 = 166MHz
 * Fout = 166MHz / 2      = 83MHz
 * Post Divisor = 2
 * XRCC = (M - 2) = 57  = 0x38
 * XRCD = (N - 2) = 3   = 0x03
 * XRCE =                 0x90
 *
 * Note Bit7 enables the clock source from the VCO
 *
 */

/*******************************************************************
 * Chips struct
 *******************************************************************/
struct ctfb_chips_properties {
	int device_id;		/* PCI Device ID */
	unsigned long max_mem;	/* memory for frame buffer */
	int vld_set;		/* value of VLD if bit2 in clock control is set */
	int vld_not_set;	/* value of VLD if bit2 in clock control is set */
	int mn_diff;		/* difference between M/N Value + mn_diff = M/N Register */
	int mn_min;		/* min value of M/N Value */
	int mn_max;		/* max value of M/N Value */
	int vco_min;		/* VCO Min in MHz */
	int vco_max;		/* VCO Max in MHz */
};

static const struct ctfb_chips_properties chips[] = {
	{PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
	{PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220},	/* NOT TESTED */
	{0, 0, 0, 0, 0, 0, 0, 0, 0}	/* Terminator */
};

/*
 * The Graphic Device
 */
GraphicDevice ctfb;

/*******************************************************************************
*
* Low Level Routines
*/

/*******************************************************************************
*
* Read CT ISA register
*/
#ifdef VGA_DEBUG
static unsigned char
ctRead (unsigned short index)
{
	GraphicDevice *pGD = (GraphicDevice *) & ctfb;
	if (index == CT_AR_O)
		/* synch the Flip Flop */
		in8 (pGD->isaBase + CT_STATUS_REG1_O);

	return (in8 (pGD->isaBase + index));
}
#endif
/*******************************************************************************
*
* Write CT ISA register
*/
static void
ctWrite (unsigned short index, unsigned char val)
{
	GraphicDevice *pGD = (GraphicDevice *) & ctfb;