ram256x8.vhd

《CPLDFPGA嵌入式应用开发技术白金手册》源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
PACKAGE ram_constants IS
  constant DATA_WIDTH : INTEGER := 8;
  constant ADDR_WIDTH : INTEGER := 8;
END ram_constants; 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY work;
USE work.ram_constants.ALL;
ENTITY ram256x8 IS
   PORT(
      data: IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
      address: IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
      we, inclock, outclock: IN STD_LOGIC;

      q: OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 DOWNTO 0));
END ram256x8;

ARCHITECTURE example OF ram256x8 IS

BEGIN
   inst_1: lpm_ram_dq
      GENERIC MAP (lpm_widthad => ADDR_WIDTH,
         lpm_width => DATA_WIDTH)
      PORT MAP (data => data, address => address, we => we,
         inclock => inclock, outclock => outclock, q => q);
END example;