mydivider.vhd

《CPLDFPGA嵌入式应用开发技术白金手册》源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mydivider is
port(divident:in std_logic_vector(3 downto 0);
	dividor:in std_logic_vector(3 downto 0);
	carrybit:out std_logic;
	result:out std_logic_vector(3 downto 0);
	residual:out std_logic_vector(3 downto 0));
end mydivider;
architecture behav of mydivider is 
--signal c,d:std_logic_vector(3 downto 0);
begin
process(divident,dividor)
variable counter_1:integer;
variable c,d,a,b,e,f,sig_1:std_logic_vector(3 downto 0);
begin
a:=divident;
b:=dividor;
e:=a;
f:=b;
counter_1:=0;
if(b="0000")then 
	c:="1111";
	d:="1111";
	carrybit<='1';
else
	if(a<b)then
		c:="0000";
		d:=a;
		carrybit<='0';
	else
		if(a="0000")then
			c:="0000";
			d:="0000";
		else
			for i in 3 downto 0 loop
					if(f(3)='0')then
						for j in 3 downto 1 loop
							f(j):=f(j-1);
						end loop;
						f(0):='0';
						counter_1:=counter_1+1;
					end if;
			end loop;
			for i in 3 downto 0 loop
					if(i>counter_1)then
						c(i):='0';
					elsif (e<f)then 
						for j in 0 to 2 loop
							f(j):=f(j+1);
						end loop;
						f(3):='0';
						c(i):='0';
					else
						e:=e-f;
						c(i):='1';
						for j in 0 to 2 loop
							f(j):=f(j+1);
						end loop;
						f(3):='0';
					end if;
			end loop;
			d:=e;
		end if;
		carrybit<='0';
	end if;
end if;
result<=c;
residual<=d;
end process;
end behav;