dds_dds.vhd

《CPLDFPGA嵌入式应用开发技术白金手册》源代码

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;

ENTITY dds_dds IS
	port(ftw: in std_logic_vector(23 downto 0);					--频率控制字
		 clk: in std_logic;										--系统时钟
		 rec: in std_logic;										--接收信号使能
		 out_q:	out std_logic_vector(9 downto 0);				--幅度值输出
		 ack: out std_logic);									--接收应答信号
END dds_dds;

ARCHITECTURE beh of dds_dds is
signal phase_adder,frq_reg:std_logic_vector(23 downto 0);
signal rom_address,address:std_logic_vector(9 downto 0);
signal rom_out:std_logic_vector(9 downto 0);
signal s_1,s_2,a_1,a_2:std_logic;
signal a:std_logic;
component dds_dds_rom											--定义ROM元件
	PORT(address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		 q		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0));
end component;
begin
	data: dds_dds_rom port map(address,rom_out);
	datain: process(clk)										--数据输入部分
	begin
	if(clk'event and clk='1') then								--clk上升沿触发
		if(rec='1') then										--rec为1则读取ftw数据并将应答信号ack置1
			frq_reg<=ftw;									  
			ack<='1';										  
			a<='1';												--a与ack内容相同在判断时使用
		end if;												  
		if(a='1') then											--检测到上一个周期ack为1，则将其复位
			ack<='0';										  
			a<='0';											  
		end if;
	end if;
	end process;

	phase_add: process(clk)										--相位累加部分
	begin
		if(clk'event and clk='1') then							--clk上升沿触发
			phase_adder<=phase_adder+frq_reg;					--进行相位累加
			rom_address(0)<=phase_adder(12);				
			rom_address(1)<=phase_adder(13);
			rom_address(2)<=phase_adder(14);
			rom_address(3)<=phase_adder(15);
			rom_address(4)<=phase_adder(16);
			rom_address(5)<=phase_adder(17);
			rom_address(6)<=phase_adder(18);
			rom_address(7)<=phase_adder(19);
			rom_address(8)<=phase_adder(20);
			rom_address(9)<=phase_adder(21);
			s_2<=phase_adder(22);
			s_1<=phase_adder(23);								--将上一个累加值的高12位送出
		end if;
	end process;
	
	lookfor_rom: process(clk)									--ROM查找部分
	begin
		if(clk'event and clk='1') then							--clk上升沿触发
			a_1<=s_1;											--a_1和a_2比s_1和s_2落后一个周期
			a_2<=s_2;
			if(s_1='0' and s_2='0') then  						--将各区间的地址对应到0～π/2的地址
				address<=rom_address;
			elsif(s_1='0' and s_2='1') then	
				address<=NOT rom_address;	
			elsif(s_1='1' and s_2='0') then
				address<=rom_address;
			elsif(s_1='1' and s_2='1') then
				address<=NOT rom_address;
			end if;												-- NOT rom_address＝3FF－rom_address

			if(a_1='0' and a_2='0') then  						--将各区间的幅度对应到0～π/2的幅度
				out_q<=rom_out;									--由于幅度比地址输出慢一个周期所以用
																-- a_1和a_2进行判断，a_1和a_2比s_1
																--和s_2落后一个时钟周期
			elsif(a_1='0' and a_2='1') then	
				out_q<=rom_out;
			elsif(a_1='1' and a_2='0') then
				out_q<=NOT rom_out+"0000000001";
			elsif(a_1='1' and a_2='1') then
				out_q<=NOT rom_out+"0000000001";
			end if;												--负数通过正数取反再加1得到
		end if;
	end process;

end beh;