fangbo.vhd

《CPLDFPGA嵌入式应用开发技术白金手册》源代码

--fangbo 模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fangbo is
port(
      clk   :in std_logic;
      dout  : out std_logic
     );
end fangbo;
architecture behav of fangbo is
begin
      process(clk)
      variable count: std_logic_vector(4 downto 0);
      variable flag: boolean;
      begin
            if clk'event and clk='0' then
                    count:=count+1;
                    if count="11111" then
                       flag:= not flag;
                    end if;
                    case flag is
                    when false=>dout<='1';
                    when true=>dout<='0';
                    end case;
            end if;
      end process;
end behav;