sel2.vhd

《CPLDFPGA嵌入式应用开发技术白金手册》源代码

--SEL2 模块
library ieee;
use ieee.std_logic_1164.all;
entity sel2 is
port(
     kin1,kin2: in std_logic;
     sel:in std_logic;
     fout1,fout2,aout1,aout2: out std_logic
    );
end sel2;
architecture beh of sel2 is
begin
    process(sel)
    begin
       case sel is
       when '0' =>fout1<=kin1;
                  fout2<=kin2;
       when '1' =>aout1<=kin1;
				  aout2<=kin2;
        when others =>null;
        end case;
     end process;
end beh;