myrisc2.vhd

《CPLDFPGA嵌入式应用开发技术白金手册》源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package dp16 is
		procedure int_to_bits (int : in integer; bits : out std_logic_vector);
end dp16;
package body dp16 is
procedure int_to_bits (int : in integer; bits : out std_logic_vector(31 downto 0)) is
variable temp : integer;
variable result : std_logic_vector(31 downto 0);
begin
temp:=int;
result:=conv_std_logic_vector(temp,32);
bits:=result;
end int_to_bits;
end dp16;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.dp16.all;
entity myrisc2 is
	port(instruction:in std_logic_vector(1 downto 0);
		a:in std_logic_vector(31 downto 0);
		c:out std_logic_vector(31 downto 0));
end myrisc2;
architecture behav of myrisc2 is
begin
process(a)
	variable q:integer;
	variable b:std_logic_vector(31 downto 0);
begin
case instruction is
when "00" =>
q:=conv_integer(a);
int_to_bits(q,b);
c<=b;
when others =>
c<="00000000000000000000000000000000";
end case;
end process;
end behav;