fredivn.vhd

《CPLDFPGA嵌入式应用开发技术白金手册》源代码

package width is
constant N:integer:=8;
end width;
USE work.width.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn is
GENERIC (N:integer:=6);
port(clkin:in std_logic;
	clkout :out std_logic);
end fredivn;
architecture behav of fredivn is
signal count :integer;
begin
process(clkin)
begin
if(clkin'event and clkin='1')then
	if(count<N-1)then
		count<=count+1;
	else
		count<=0;
	end if;
	if(count<N/2)then 
		clkout<='1';
	else 
		clkout<='0';
	end if;
end if;
end process;
end behav;