📄 led.map.rpt
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Analysis & Synthesis report for LED
Thu May 31 13:19:52 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis Equations
8. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu May 31 13:19:52 2007 ;
; Quartus II Version ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name ; LED ;
; Top-level Entity Name ; LED ;
; Family ; MAX7000S ;
; Total macrocells ; 14 ;
; Total pins ; 14 ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+------------------+---------------+
; Device ; EPM7128STC100-10 ; ;
; Top-level entity name ; LED ; LED ;
; Family name ; MAX7000S ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+----------------------------------------------------------------------+------------------+---------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------------------+
; LED.v ; yes ; User Verilog HDL File ; F:/xtgkw/新项目/usb+mcu+cpld+ad+da/光盘/CPLD部分/实验一：点亮LED（发光二极管）/exp1/LED.v ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 14 ;
; Total registers ; 0 ;
; I/O pins ; 14 ;
; Maximum fan-out node ; ~VCC~0 ;
; Maximum fan-out ; 1 ;
; Total fan-out ; 14 ;
; Average fan-out ; 0.50 ;
+----------------------+----------------------+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |LED ; 14 ; 14 ; |LED ;
+----------------------------+------------+------+---------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/xtgkw/新项目/usb+mcu+cpld+ad+da/光盘/CPLD部分/实验一：点亮LED（发光二极管）/exp1/LED.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Thu May 31 13:19:52 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LED -c LED
Info: Found 1 design units, including 1 entities, in source file LED.v
Info: Found entity 1: LED
Info: Elaborating entity "LED" for the top level hierarchy
Warning: Output pins are stuck at VCC or GND
Warning: Pin "LED[0]" stuck at VCC
Warning: Pin "LED[1]" stuck at GND
Warning: Pin "LED[2]" stuck at GND
Warning: Pin "LED[3]" stuck at VCC
Warning: Pin "LED[4]" stuck at VCC
Warning: Pin "LED[5]" stuck at VCC
Warning: Pin "LED[6]" stuck at GND
Warning: Pin "LED[7]" stuck at VCC
Warning: Pin "LED[8]" stuck at VCC
Warning: Pin "LED[9]" stuck at GND
Warning: Pin "LED[10]" stuck at GND
Warning: Pin "LED[11]" stuck at VCC
Warning: Pin "LED[12]" stuck at VCC
Warning: Pin "LED[13]" stuck at VCC
Info: Implemented 28 device resources after synthesis - the final resource count might be different
Info: Implemented 0 input pins
Info: Implemented 14 output pins
Info: Implemented 14 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings
Info: Processing ended: Thu May 31 13:19:52 2007
Info: Elapsed time: 00:00:01
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