lpm.vhd

《数字信号处理的FPGA实现》代码

   begin
       if ACLR =  '1' then
              IQ <= (OTHERS => '0');
       elsif ASET = '1' then
           if LPM_AVALUE = UNUSED then
              IQ <= (OTHERS => '1');
           else
              IAVALUE := str_to_int(LPM_AVALUE);
              IQ <= conv_std_logic_vector(IAVALUE, LPM_WIDTH);
           end if;
       elsif CLOCK'event and CLOCK = '1' then
          if ENABLE = '1' then
                  if SCLR = '1' then
                     IQ <= (OTHERS => '0');
                  elsif SSET = '1' then
                     if LPM_SVALUE = UNUSED then
                       IQ <= (OTHERS => '1');
                     else
                       ISVALUE := str_to_int(LPM_SVALUE);
                       IQ <= conv_std_logic_vector(ISVALUE, LPM_WIDTH);
                     end if;
                  elsif LOAD = '0' then
                       IQ <= (IQ(LPM_WIDTH-1 downto 0) & SHIFTIN);
                  else
                       IQ(LPM_WIDTH-1 downto 0) <= DATA;
                  end if;
           end if;
       end if;
   end process;

   Q <= IQ(LPM_WIDTH-1 downto 0);
   SHIFTOUT <= IQ(LPM_WIDTH);

end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;

entity LPM_LATCH is
     generic (LPM_WIDTH : positive;
              LPM_AVALUE : string := UNUSED;
              LPM_PVALUE : string := UNUSED;
              LPM_TYPE: string := L_LATCH);
     port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
           GATE : in std_logic;
           ASET : in std_logic;
           ACLR : in std_logic;
           Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_LATCH;

architecture LPM_SYN of LPM_LATCH is

begin

   process (DATA,GATE,ACLR,ASET)
   variable IAVALUE : integer;
   begin
       if ACLR =  '1' then
              Q <= (OTHERS => '0');
       elsif ASET = '1' then
          if LPM_AVALUE = UNUSED then
              Q <= (OTHERS => '1');
          else
              IAVALUE := str_to_int(LPM_AVALUE);
              Q <= conv_std_logic_vector(IAVALUE, LPM_WIDTH);
          end if;
       elsif GATE = '1' then
              Q <= DATA;
       end if;
   end process;

end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;

entity LPM_INPAD is
    generic (LPM_WIDTH : positive;
             LPM_TYPE: string := L_INPAD);
    port (PAD : in std_logic_vector(LPM_WIDTH-1 downto 0);
          RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_INPAD;

architecture LPM_SYN of LPM_INPAD is
begin

 RESULT <=  PAD;

end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;

entity LPM_OUTPAD is
    generic (LPM_WIDTH : positive;
             LPM_TYPE: string := L_OUTPAD);
    port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
          PAD : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_OUTPAD;

architecture LPM_SYN of LPM_OUTPAD is
begin

   PAD <= DATA;

end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;

entity LPM_BIPAD is
    generic (LPM_WIDTH : positive;
             LPM_TYPE: string := L_BIPAD);
    port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
          ENABLE : in std_logic;
          RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
          PAD : inout std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_BIPAD;

architecture LPM_SYN of LPM_BIPAD is

begin

    process(DATA,PAD,ENABLE)
    begin
        if ENABLE = '1' then
           PAD <= DATA;
           RESULT <= (OTHERS => 'Z');
        else
           RESULT <= PAD;
           PAD <= (OTHERS => 'Z');
        end if;
    end process;

end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;


entity LPM_CLSHIFT is
    generic (LPM_WIDTH : positive;
             LPM_WIDTHDIST : positive;
             LPM_SHIFTTYPE : string;
             LPM_TYPE: string := L_CLSHIFT);
    port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
          DISTANCE : in std_logic_vector(LPM_WIDTHDIST-1 downto 0);
          DIRECTION : in std_logic;
          UNDERFLOW : out std_logic;
          OVERFLOW : out std_logic;
          RESULT: out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_CLSHIFT;

architecture LPM_SYN of LPM_CLSHIFT is
signal IRESULT : std_logic_vector(LPM_WIDTH-1 downto 0);
signal TMPDATA : std_logic_vector(LPM_WIDTHDIST downto 1);
begin

   process(DATA,DISTANCE,DIRECTION)
   begin

      TMPDATA <= (OTHERS => '0');
      if LPM_SHIFTTYPE = ARITHMETIC then
         if DIRECTION = '0' then
            IRESULT <= conv_std_logic_vector((conv_integer(DATA) * (2**LPM_WIDTHDIST)), LPM_WIDTH);
         else
            IRESULT <= conv_std_logic_vector((conv_integer(DATA) / (2**LPM_WIDTHDIST)), LPM_WIDTH);
         end if;

      elsif LPM_SHIFTTYPE = ROTATE then
         if DIRECTION = '0' then
            IRESULT <= (DATA(LPM_WIDTH-LPM_WIDTHDIST-1 downto 0) &
                        DATA(LPM_WIDTH-1 downto LPM_WIDTH-LPM_WIDTHDIST));
         else
             IRESULT <= (DATA(LPM_WIDTHDIST-1 downto 0) &
                        DATA(LPM_WIDTH-1 downto LPM_WIDTHDIST));
         end if;

      else
         if DIRECTION =  '1' then
             IRESULT <= (DATA(LPM_WIDTH-LPM_WIDTHDIST-1 downto 0) & TMPDATA);
         else
             IRESULT(LPM_WIDTH-LPM_WIDTHDIST-1 downto 0) <= DATA(LPM_WIDTH-1 downto LPM_WIDTHDIST);
             IRESULT(LPM_WIDTH-1 downto LPM_WIDTH-LPM_WIDTHDIST) <= (OTHERS => '0');

         end if;
      end if;

   end process;

   process(IRESULT)
   begin
      if LPM_SHIFTTYPE = LOGICAL or LPM_SHIFTTYPE = ROTATE then
         if IRESULT > 2 ** (LPM_WIDTH) then
            OVERFLOW <= '1';
         else
            OVERFLOW <= '0';
         end if;

         if IRESULT = 0 then
            UNDERFLOW <= '1';
         else
            UNDERFLOW <= '0';
         end if;
      else
         OVERFLOW <= '0';
         UNDERFLOW <= '0';
      end if;

   end process;

   RESULT <= IRESULT;

end LPM_SYN;

library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;

entity LPM_AND is
    generic (LPM_WIDTH : positive ;
             LPM_SIZE : positive );
    port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0,LPM_WIDTH-1 downto 0);
          RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_AND;

architecture LPM_SYN of LPM_AND is

signal RESULT_INT : std_logic_2d(LPM_SIZE-1 downto 0,LPM_WIDTH-1 downto 0);

begin

   L1 : for i in 0 to LPM_WIDTH-1 generate
           RESULT_INT(0,i) <= DATA(0,i);
        L2:      for j in 0 to LPM_SIZE-2 generate
                    RESULT_INT(j+1,i) <=  RESULT_INT(j,i) and DATA(j+1,i);
           L3:      if j = LPM_SIZE-2 generate
                       RESULT(i) <= RESULT_INT(LPM_SIZE-1,i);
                    end generate L3;
                end generate L2;
        end generate L1;

end LPM_SYN;

library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;

entity LPM_OR is
    generic (LPM_WIDTH : positive ;
             LPM_SIZE : positive );
    port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0,LPM_WIDTH-1 downto 0);
          RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_OR;

architecture LPM_SYN of LPM_OR is

signal RESULT_INT : std_logic_2d(LPM_SIZE-1 downto 0,LPM_WIDTH-1 downto 0);

begin

   L1 : for i in 0 to LPM_WIDTH-1 generate
           RESULT_INT(0,i) <= DATA(0,i);
        L2 : for j in 0 to LPM_SIZE-2 generate
                RESULT_INT(j+1,i) <=  RESULT_INT(j,i) or DATA(j+1,i);
            L3 : if j = LPM_SIZE-2 generate
                     RESULT(i) <= RESULT_INT(LPM_SIZE-1,i);
            end generate L3;
        end generate L2;
   end generate L1;

end LPM_SYN;

library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;

entity LPM_XOR is
    generic (LPM_WIDTH : positive ;
             LPM_SIZE : positive );
    port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0,LPM_WIDTH-1 downto 0);
          RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_XOR;

architecture LPM_SYN of LPM_XOR is

signal RESULT_INT : std_logic_2d(LPM_SIZE-1 downto 0,LPM_WIDTH-1 downto 0);

begin

   L1 : for i in 0 to LPM_WIDTH-1 generate
            RESULT_INT(0,i) <= DATA(0,i);
       L2: for j in 0 to LPM_SIZE-2 generate
               RESULT_INT(j+1,i) <=  RESULT_INT(j,i) xor DATA(j+1,i);
          L3:  if j = LPM_SIZE-2 generate
                   RESULT(i) <= RESULT_INT(LPM_SIZE-1,i);
          end generate L3;
       end generate L2;
  end generate L1;

end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;

entity LPM_MUX is
    generic (LPM_WIDTH: positive ;
             LPM_WIDTHS : positive;
             LPM_SIZE: positive;
             LPM_PIPELINE : integer := 0);
    port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
          ACLR : in std_logic := '0';
          CLOCK : in std_logic := '0';
          SEL : in std_logic_vector(LPM_WIDTHS-1 downto 0);
          RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_MUX;

architecture LPM_SYN of LPM_MUX is
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTH-1 downto 0);

begin

   process (ACLR, CLOCK, SEL, DATA)
   variable resulttmp : t_resulttmp;
   variable ISEL : integer;
   begin
       if LPM_PIPELINE >= 0 then
          ISEL := conv_integer(SEL);

          for i in 0 to LPM_WIDTH-1 loop
              resulttmp(LPM_PIPELINE)(i) := DATA(ISEL,i);
          end loop;

          if LPM_PIPELINE > 0 then
             if ACLR = '1' then
                 for i in 0 to LPM_PIPELINE loop
                     resulttmp(i) := (OTHERS => '0');
                 end loop;
             elsif CLOCK'event and CLOCK = '1' then
                 resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);

             end if;
          end if;

          RESULT <= resulttmp(0);
       end if;

   end process;

end LPM_SYN;