lpm.vhd

《数字信号处理的FPGA实现》代码

entity LPM_MULT_UNSIGNED is
   generic (LPM_WIDTHA : positive;
            LPM_WIDTHB : positive;
            LPM_WIDTHS : positive;
            LPM_WIDTHP : positive;
            LPM_PIPELINE : integer := 0);
   port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
         DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
         ACLR : in std_logic := '0';
         CLOCK : in std_logic := '0';
         SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0);
         RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end LPM_MULT_UNSIGNED;

architecture LPM_SYN of LPM_MULT_UNSIGNED is
signal FP : std_logic_vector(LPM_WIDTHS-1 downto 0);
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTHP-1 downto 0);
begin
   process (CLOCK, ACLR, DATAA, DATAB, SUM)
   variable resulttmp : t_resulttmp;
   begin
       if LPM_PIPELINE >= 0 then
          if LPM_WIDTHP >= LPM_WIDTHS then
            resulttmp(LPM_PIPELINE) := (DATAA * DATAB) + SUM;
          else
            FP <= (DATAA * DATAB) + SUM;
            resulttmp(LPM_PIPELINE) := FP(LPM_WIDTHS-1 downto LPM_WIDTHS-LPM_WIDTHP);
          end if;

          if LPM_PIPELINE > 0 then
             if ACLR = '1' then
                for i in 0 to LPM_PIPELINE loop
                   resulttmp(i) := (OTHERS => '0');
                end loop;
             elsif CLOCK'event and CLOCK = '1' then
                resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
             end if;
          end if;
       end if;

       RESULT <= resulttmp(0);
   end process;

end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;

entity LPM_MULT is
   generic (LPM_WIDTHA : positive;
            LPM_WIDTHB : positive;
            LPM_WIDTHS : positive;
            LPM_REPRESENTATION : string := UNSIGNED ;
            LPM_WIDTHP : positive;
            LPM_TYPE: string := L_MULT;
            LPM_PIPELINE : integer := 0;
            LPM_HINT : string := UNUSED);
   port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
         DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
         ACLR : in std_logic := '0';
         CLOCK : in std_logic := '0';
         SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0);
         RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end LPM_MULT;

architecture LPM_SYN of LPM_MULT is

     component LPM_MULT_UNSIGNED
       generic (LPM_WIDTHA : positive;
            LPM_WIDTHB : positive;
            LPM_WIDTHS : positive;
            LPM_WIDTHP : positive;
            LPM_PIPELINE : integer := 0);
       port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
            DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
            ACLR : in std_logic := '0';
            CLOCK : in std_logic := '0';
            SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0);
            RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
     end component;

     component LPM_MULT_SIGNED
       generic (LPM_WIDTHA : positive;
            LPM_WIDTHB : positive;
            LPM_WIDTHS : positive;
            LPM_WIDTHP : positive;
            LPM_PIPELINE : integer := 0);
       port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
            DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
            ACLR : in std_logic := '0';
            CLOCK : in std_logic := '0';
            SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0);
            RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
     end component;

begin

L1: if LPM_REPRESENTATION = UNSIGNED generate

       U1: LPM_MULT_UNSIGNED generic map (LPM_WIDTHA => LPM_WIDTHA,
                       LPM_WIDTHB => LPM_WIDTHB, LPM_WIDTHS => LPM_WIDTHS,
                       LPM_WIDTHP => LPM_WIDTHP, LPM_PIPELINE => LPM_PIPELINE)
          port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR,
                    SUM => SUM, CLOCK => CLOCK, RESULT => RESULT);
    end generate;

L2: if LPM_REPRESENTATION = SIGNED generate

       U1: LPM_MULT_SIGNED generic map (LPM_WIDTHA => LPM_WIDTHA,
                       LPM_WIDTHB => LPM_WIDTHB, LPM_WIDTHS => LPM_WIDTHS,
                       LPM_WIDTHP => LPM_WIDTHP, LPM_PIPELINE => LPM_PIPELINE)
          port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR,
                    SUM => SUM, CLOCK => CLOCK, RESULT => RESULT);
    end generate;

end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;

entity LPM_ABS is
    generic (LPM_WIDTH : positive := 2;
             LPM_TYPE: string := L_ABS);
    port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
          RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
          OVERFLOW: out std_logic);
end LPM_ABS;

architecture LPM_SYN of LPM_ABS is
begin

   process(DATA)
   begin

       if (DATA = -2 ** (LPM_WIDTH-1)) then
           OVERFLOW <= '1';
           RESULT <= (OTHERS => 'X');
       elsif DATA < 0 then
           RESULT <= 0 - DATA;
           OVERFLOW <= '0';
       else
           RESULT <= DATA;
           OVERFLOW <= '0';
       end if;

   end process;

end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;

entity LPM_COUNTER is
     generic (LPM_WIDTH : positive;
              LPM_MODULUS : string := UNUSED;
              LPM_DIRECTION : string := UNUSED;
              LPM_AVALUE : string := UNUSED;
              LPM_SVALUE : string := UNUSED;
              LPM_TYPE: string := L_COUNTER;
              LPM_PVALUE : string := UNUSED;
              LPM_HINT : string := UNUSED);
     port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
           CLOCK : in std_logic;
           CLK_EN : in std_logic;
           CNT_EN : in std_logic;
           UPDOWN : in std_logic;
           SLOAD : in std_logic;
           SSET : in std_logic;
           SCLR : in std_logic;
           ALOAD : in std_logic;
           ASET : in std_logic;
           ACLR : in std_logic;
	   EQ : out std_logic;
           Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_COUNTER;

architecture LPM_SYN of LPM_COUNTER is
signal COUNT : std_logic_vector(LPM_WIDTH-1 downto 0);

begin

   Counter: process (CLOCK,ACLR,ASET,ALOAD,DATA)
   variable IAVALUE, ISVALUE : integer;
   begin
       if ACLR =  '1' then
              COUNT <= (OTHERS => '0');
       elsif ASET = '1' then
          if LPM_AVALUE = UNUSED then
              COUNT <= (OTHERS => '1');
          else
              IAVALUE := str_to_int(LPM_AVALUE);
              COUNT <= conv_std_logic_vector(IAVALUE, LPM_WIDTH);
          end if;
       elsif ALOAD = '1' then
              COUNT <= DATA;
       elsif CLOCK'event and CLOCK = '1' then
          if CLK_EN = '1' then
              if SCLR = '1' then
                 COUNT <= (OTHERS => '0');
              elsif SSET = '1' then
                 if LPM_SVALUE = UNUSED then
                     COUNT <= (OTHERS => '1');
                 else
                     ISVALUE := str_to_int(LPM_SVALUE);
                     COUNT <= conv_std_logic_vector(ISVALUE, LPM_WIDTH);
                 end if;
              elsif SLOAD = '1' then
                    COUNT <= DATA;
              elsif CNT_EN = '1' then
                 if LPM_DIRECTION = UNUSED then
                    if UPDOWN = '1' then
                        COUNT <= COUNT + 1;
                    else
                        COUNT <= COUNT - 1;
                    end if;
                 elsif LPM_DIRECTION = UP then
                    COUNT <= COUNT + 1;
                 elsif LPM_DIRECTION = DOWN then
                    COUNT <= COUNT - 1;
                 else
                    COUNT <= COUNT + 1; --Anything other than legal values.
                 end if;
              end if;
           end if;
       end if;
   end process Counter;


   Decode: process (COUNT)
   begin
       if LPM_MODULUS = UNUSED then
          if (COUNT = (2 ** LPM_WIDTH) -1) then
             EQ <= '1';
          else
             EQ <= '0';
          end if;
       else
          if COUNT = str_to_int(LPM_MODULUS)-1 then
             EQ <= '1';
          else
             EQ <= '0';
          end if;
       end if;
   end process Decode;

   Q <= COUNT;

end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;

entity LPM_FF is
     generic (LPM_WIDTH : positive;
              LPM_AVALUE : string := UNUSED;
              LPM_SVALUE : string := UNUSED;
              LPM_FFTYPE : string := FFTYPE_DFF;
              LPM_TYPE: string := L_FF);
     port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
           CLOCK : in std_logic;
           ASET : in std_logic;
           ACLR : in std_logic;
           ALOAD: in std_logic;
           SSET : in std_logic;
           SCLR : in std_logic;
           SLOAD : in std_logic;
           ENABLE : in std_logic;
           Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_FF;

architecture LPM_SYN of LPM_FF is
signal IQ : std_logic_vector(LPM_WIDTH-1 downto 0);
begin

   process (DATA,CLOCK,ACLR,ASET,ALOAD)
   variable IAVALUE, ISVALUE : integer;
   begin
       if ACLR =  '1' then
              IQ <= (OTHERS => '0');
       elsif ASET = '1' then
          if LPM_AVALUE = UNUSED then
              IQ <= (OTHERS => '1');
          else
              IAVALUE := str_to_int(LPM_AVALUE);
              IQ <= conv_std_logic_vector(IAVALUE, LPM_WIDTH);
          end if;
       elsif ALOAD = '1' then
          if LPM_FFTYPE = FFTYPE_TFF then
              IQ <= DATA;
          end if;
       elsif CLOCK'event and CLOCK = '1' then
          if ENABLE = '1' then
              if SCLR = '1' then
                 IQ <= (OTHERS => '0');
              elsif SSET = '1' then
                 if LPM_SVALUE = UNUSED then
                   IQ <= (OTHERS => '1');
                 else
                   ISVALUE := str_to_int(LPM_SVALUE);
                   IQ <= conv_std_logic_vector(ISVALUE, LPM_WIDTH);
                 end if;
              elsif  SLOAD = '1' then
                 if LPM_FFTYPE = FFTYPE_TFF then
                   IQ <= DATA;
                 end if;
              else
                 if LPM_FFTYPE = FFTYPE_TFF then
                   for i in 0 to LPM_WIDTH-1 loop
                     if DATA(i) = '1' then
                        IQ(i) <= not IQ(i);
                     end if;
                   end loop;
                 else
                   IQ <= DATA;
                 end if;
              end if;
           end if;
       end if;
   end process;

   Q <= IQ;

end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;

entity LPM_SHIFTREG is
     generic (LPM_WIDTH : positive;
              LPM_AVALUE : string := UNUSED;
              LPM_SVALUE : string := UNUSED;
              LPM_PVALUE : string := UNUSED;
              LPM_DIRECTRION : string := UNUSED;
              LPM_TYPE: string := L_SHIFTREG);
     port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
           CLOCK : in std_logic;
           ASET : in std_logic;
           ACLR : in std_logic;
           SSET : in std_logic;
           SCLR : in std_logic;
           ENABLE : in std_logic;
           LOAD : in std_logic;
           SHIFTIN : in std_logic;
           SHIFTOUT : out std_logic;
           Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_SHIFTREG;

architecture LPM_SYN of LPM_SHIFTREG is
signal IQ : std_logic_vector(LPM_WIDTH downto 0);
begin

   process (CLOCK,ACLR,ASET,SCLR)
   variable IAVALUE, ISVALUE : integer;