📄 lpm.vhd
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--------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be freely
-- copied and/or distributed at no cost. Any persons using this file for
-- any purpose do so at their own risk, and are responsible for the results
-- of such use. Altera Corporation does not guarantee that this file is
-- complete, correct, or fit for any particular purpose. NO WARRANTY OF
-- ANY KIND IS EXPRESSED OR IMPLIED. This notice must accompany any copy
-- of this file.
--
--------------------------------------------------------------------------
-- LPM Synthesizable Models (Support sting type generic)
--------------------------------------------------------------------------
-- Version 1.3 Date 07/30/96
--
-- Modification History
--
-- 1. Changed the DEFAULT value to UNUSED for LPM_SVALUE, LPM_AVALUE,
-- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION,
-- and LPM_PVALUE
--
-- 2. Added the two dimentional port components (AND, OR, XOR, and MUX).
--------------------------------------------------------------------------
-- Excluded Functions:
--
-- LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, and LPM_FSM, and LPM_TTABLE.
--
--------------------------------------------------------------------------
-- Assumptions:
--
-- 1. All ports and signal types are std_logic or std_logic_vector
-- from IEEE 1164 package.
-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed
-- package are assumed to be accessible from IEEE library.
-- 3. lpm_component_package must be accessible from library work.
-- 4. LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,
-- LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE default value is
-- string UNUSED.
--------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_CONSTANT is
generic (LPM_WIDTH : positive;
LPM_CVALUE: natural;
LPM_TYPE: string := L_CONSTANT;
LPM_STRENGTH : string := UNUSED);
port (RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_CONSTANT;
architecture LPM_SYN of LPM_CONSTANT is
begin
RESULT <= conv_std_logic_vector(LPM_CVALUE, LPM_WIDTH);
end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_INV is
generic (LPM_WIDTH : positive;
LPM_TYPE: string := L_INV);
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_INV;
architecture LPM_SYN of LPM_INV is
begin
RESULT <= not DATA;
end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_BUSTRI is
generic (LPM_WIDTH : positive;
LPM_TYPE: string := L_BUSTRI);
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ENABLEDT : in std_logic;
ENABLETR : in std_logic;
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
TRDATA : inout std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_BUSTRI;
architecture LPM_SYN of LPM_BUSTRI is
begin
process(DATA,TRDATA,ENABLETR,ENABLEDT)
begin
if ENABLEDT = '0' and ENABLETR = '1' then
RESULT <= TRDATA;
TRDATA <= (OTHERS => 'Z');
elsif ENABLEDT = '1' and ENABLETR = '0' then
RESULT <= (OTHERS => 'Z');
TRDATA <= DATA;
elsif ENABLEDT = '1' and ENABLETR = '1' then
RESULT <= DATA;
TRDATA <= DATA;
else
RESULT <= (OTHERS => 'Z');
TRDATA <= (OTHERS => 'Z');
end if;
end process;
end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_DECODE is
generic (LPM_WIDTH : positive;
LPM_DECODES : natural;
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := L_DECODE);
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
ENABLE : in std_logic;
EQ : out std_logic_vector(LPM_DECODES-1 downto 0));
end LPM_DECODE;
architecture LPM_SYN of LPM_DECODE is
type t_eqtmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_DECODES-1 downto 0);
begin
process(ACLR, CLOCK, DATA,ENABLE)
variable eqtmp : t_eqtmp;
begin
if LPM_PIPELINE >= 0 then
for i in 0 to LPM_DECODES-1 loop
if conv_integer(DATA) = i then
if ENABLE = '1' then
eqtmp(LPM_PIPELINE)(i) := '1';
else
eqtmp(LPM_PIPELINE)(i) := '0';
end if;
else
eqtmp(LPM_PIPELINE)(i) := '0';
end if;
end loop;
if LPM_PIPELINE > 0 then
if ACLR = '1' then
for i in 0 to LPM_PIPELINE loop
eqtmp(i) := (OTHERS => '0');
end loop;
elsif CLOCK'event and CLOCK = '1' then
eqtmp(0 to LPM_PIPELINE - 1) := eqtmp(1 to LPM_PIPELINE);
end if;
end if;
end if;
EQ <= eqtmp(0);
end process;
end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
entity LPM_ADD_SUB_SIGNED is
generic (LPM_WIDTH : positive;
LPM_PIPELINE : integer := 0;
LPM_DIRECTION : string);
port (DATAA: in std_logic_vector(LPM_WIDTH downto 1);
DATAB: in std_logic_vector(LPM_WIDTH downto 1);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CIN: in std_logic;
ADD_SUB: in std_logic;
RESULT: out std_logic_vector(LPM_WIDTH downto 1);
COUT: out std_logic;
OVERFLOW: out std_logic);
end LPM_ADD_SUB_SIGNED;
architecture LPM_SYN of LPM_ADD_SUB_SIGNED is
signal A, B : std_logic_vector(LPM_WIDTH downto 0);
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTH downto 0);
begin
A <= ('0' & DATAA);
B <= ('0' & DATAB);
process(ACLR, CLOCK, A, B, CIN, ADD_SUB)
variable resulttmp : t_resulttmp;
variable couttmp : std_logic_vector(0 to LPM_PIPELINE);
variable overflowtmp : std_logic_vector(0 to LPM_PIPELINE);
begin
if LPM_PIPELINE >= 0 then
if LPM_DIRECTION = ADD then
resulttmp(LPM_PIPELINE) := A + B + CIN;
elsif LPM_DIRECTION = work.LPM_COMPONENTS.SUB then
resulttmp(LPM_PIPELINE) := A - B - CIN;
else
if ADD_SUB = '1' then
resulttmp(LPM_PIPELINE) := A + B + CIN;
else
resulttmp(LPM_PIPELINE) := A - B - CIN;
end if;
end if;
if (resulttmp(LPM_PIPELINE) > (2 ** (LPM_WIDTH-1)) -1) or
(resulttmp(LPM_PIPELINE) < -2 ** (LPM_WIDTH-1)) then
overflowtmp(LPM_PIPELINE) := '1';
else
overflowtmp(LPM_PIPELINE) := '0';
end if;
couttmp(LPM_PIPELINE) := resulttmp(LPM_PIPELINE)(LPM_WIDTH);
if LPM_PIPELINE > 0 then
if ACLR = '1' then
overflowtmp := (OTHERS => '0');
couttmp := (OTHERS => '0');
for i in 0 to LPM_PIPELINE loop
resulttmp(i) := (OTHERS => '0');
end loop;
elsif CLOCK'event and CLOCK = '1' then
overflowtmp(0 to LPM_PIPELINE - 1) := overflowtmp(1 to LPM_PIPELINE);
couttmp(0 to LPM_PIPELINE - 1) := couttmp(1 to LPM_PIPELINE);
resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
end if;
end if;
COUT <= couttmp(0);
OVERFLOW <= overflowtmp(0);
RESULT <= resulttmp(0)(LPM_WIDTH-1 downto 0);
end if;
end process;
end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_ADD_SUB_UNSIGNED is
generic (LPM_WIDTH : positive;
LPM_PIPELINE : integer := 0;
LPM_DIRECTION : string);
port (DATAA: in std_logic_vector(LPM_WIDTH downto 1);
DATAB: in std_logic_vector(LPM_WIDTH downto 1);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CIN: in std_logic;
ADD_SUB: in std_logic;
RESULT: out std_logic_vector(LPM_WIDTH downto 1);
COUT: out std_logic;
OVERFLOW: out std_logic);
end LPM_ADD_SUB_UNSIGNED;
architecture LPM_SYN of LPM_ADD_SUB_UNSIGNED is
signal A, B : std_logic_vector(LPM_WIDTH downto 0);
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTH downto 0);
begin
A <= ('0' & DATAA);
B <= ('0' & DATAB);
process(ACLR, CLOCK, A, B, CIN, ADD_SUB)
variable resulttmp : t_resulttmp;
variable couttmp : std_logic_vector(0 to LPM_PIPELINE);
variable overflowtmp : std_logic_vector(0 to LPM_PIPELINE);
begin
if LPM_PIPELINE >= 0 then
if LPM_DIRECTION = ADD then
resulttmp(LPM_PIPELINE) := A + B + CIN;
elsif LPM_DIRECTION = work.LPM_COMPONENTS.SUB then
resulttmp(LPM_PIPELINE) := A - B - CIN;
else
if ADD_SUB = '1' then
resulttmp(LPM_PIPELINE) := A + B + CIN;
else
resulttmp(LPM_PIPELINE) := A - B - CIN;
end if;
end if;
if (resulttmp(LPM_PIPELINE) > (2 ** (LPM_WIDTH-1)) -1) or
(resulttmp(LPM_PIPELINE) < -2 ** (LPM_WIDTH-1)) then
overflowtmp(LPM_PIPELINE) := '1';
else
overflowtmp(LPM_PIPELINE) := '0';
end if;
couttmp(LPM_PIPELINE) := resulttmp(LPM_PIPELINE)(LPM_WIDTH);
if LPM_PIPELINE > 0 then
if ACLR = '1' then
overflowtmp := (OTHERS => '0');
couttmp := (OTHERS => '0');
for i in 0 to LPM_PIPELINE loop
resulttmp(i) := (OTHERS => '0');
end loop;
elsif CLOCK'event and CLOCK = '1' then
overflowtmp(0 to LPM_PIPELINE - 1) := overflowtmp(1 to LPM_PIPELINE);
couttmp(0 to LPM_PIPELINE - 1) := couttmp(1 to LPM_PIPELINE);
resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
end if;
end if;
COUT <= couttmp(0);
OVERFLOW <= overflowtmp(0);
RESULT <= resulttmp(0)(LPM_WIDTH-1 downto 0);
end if;
end process;
end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_ADD_SUB is
generic (LPM_WIDTH : positive;
LPM_REPRESENTATION : string;
LPM_DIRECTION : string;
LPM_TYPE: string := L_ADD_SUB;
LPM_PIPELINE : integer := 0;
LPM_HINT : string := UNUSED);
port (DATAA: in std_logic_vector(LPM_WIDTH downto 1);
DATAB: in std_logic_vector(LPM_WIDTH downto 1);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CIN: in std_logic;
ADD_SUB: in std_logic;
RESULT: out std_logic_vector(LPM_WIDTH downto 1);
COUT: out std_logic;
OVERFLOW: out std_logic);
end LPM_ADD_SUB;
architecture LPM_SYN of LPM_ADD_SUB is
component LPM_ADD_SUB_SIGNED
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