lpm_pack.vhd

《数字信号处理的FPGA实现》代码

                 LPM_HINT : string := UNUSED);
        port (RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_INV
        generic (LPM_WIDTH : positive;
                 LPM_TYPE: string := L_INV;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_BUSTRI
        generic (LPM_WIDTH : positive;
                 LPM_TYPE: string := L_BUSTRI;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
              ENABLEDT : in std_logic := '0';
              ENABLETR : in std_logic := '0';
              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
              TRIDATA : inout std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_INPAD
        generic (LPM_WIDTH : positive;
                 LPM_TYPE: string := L_INPAD;
                 LPM_HINT : string := UNUSED);
        port (PAD : in std_logic_vector(LPM_WIDTH-1 downto 0);
              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_OUTPAD
        generic (LPM_WIDTH : positive;
                 LPM_TYPE: string := L_OUTPAD;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
              PAD : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_BIPAD
        generic (LPM_WIDTH : positive;
                 LPM_TYPE: string := L_BIPAD;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
              ENABLE : in std_logic;
              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
              PAD: inout std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_CLSHIFT
        generic (LPM_WIDTH: positive;
                 LPM_WIDTHDIST: positive;
                 LPM_TYPE: string := L_CLSHIFT;
                 LPM_SHIFTTYPE: string := LOGICAL;
                 LPM_HINT : string := UNUSED);
        port (DATA: in STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
              DISTANCE: in STD_LOGIC_VECTOR(LPM_WIDTHDIST-1 downto 0);
              DIRECTION: in STD_LOGIC := '0';
              RESULT: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
              UNDERFLOW: out STD_LOGIC;
              OVERFLOW: out STD_LOGIC);
end component;

component LPM_RAM_DQ
         generic (LPM_WIDTH: positive;
                  LPM_TYPE: string := L_RAM_DQ;
                  LPM_WIDTHAD: positive;
                  LPM_NUMWORDS: string := UNUSED;
                  LPM_FILE: string := UNUSED;
                  LPM_INDATA: string := REGISTERED;
                  LPM_ADDRESS_CONTROL: string := REGISTERED;
                  LPM_OUTDATA: string := REGISTERED;
                  LPM_HINT : string := UNUSED);
         port (DATA: in STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
               ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
               WE: in STD_LOGIC := '1';
               INCLOCK: in STD_LOGIC := '1';
               OUTCLOCK: in STD_LOGIC := '1';
               Q: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
end component;

component LPM_RAM_IO
         generic (LPM_WIDTH: positive;
                  LPM_TYPE: string := L_RAM_IO;
                  LPM_WIDTHAD: positive;
                  LPM_NUMWORDS: string := UNUSED;
                  LPM_FILE: string := UNUSED;
                  LPM_INDATA: string := REGISTERED;
                  LPM_ADDRESS_CONTROL: string := REGISTERED;
                  LPM_OUTDATA: string := REGISTERED;
                  LPM_HINT : string := UNUSED);
         port (ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
               WE: in STD_LOGIC;
               INCLOCK: in STD_LOGIC := '1';
               OUTCLOCK: in STD_LOGIC := '1';
               OUTENAB: in STD_LOGIC := '1';
               MEMENAB: in STD_LOGIC := '1';
               DIO: inout STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
end component;

component LPM_ROM
         generic (LPM_WIDTH: positive;
                  LPM_TYPE: string := L_ROM;
                  LPM_WIDTHAD: positive;
                  LPM_NUMWORDS: string := UNUSED;
                  LPM_FILE: string ;
                  LPM_ADDRESS_CONTROL: string := REGISTERED;
                  LPM_OUTDATA: string := REGISTERED;
                  LPM_HINT : string := UNUSED);
          port (ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
                INCLOCK: in STD_LOGIC := '1';
                OUTCLOCK: in STD_LOGIC := '1';
                MEMENAB: in STD_LOGIC := '1';
                Q: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
end component;

component LPM_TTABLE
        generic (LPM_WIDTHIN: positive;
                 LPM_WIDTHOUT: positive;
                 LPM_TYPE: string := L_TTABLE;
                 LPM_FILE: string ;
                 LPM_TRUTHTYPE : string := FD;
                 LPM_HINT : string := UNUSED);
        port (DATA: in std_logic_vector(LPM_WIDTHIN-1 downto 0);
              RESULT: out std_logic_vector(LPM_WIDTHOUT-1 downto 0));
end component;

component LPM_FSM
        generic (LPM_WIDTHIN: positive;
                 LPM_WIDTHOUT: positive;
                 LPM_WIDTHS: positive := 1;
                 LPM_TYPE: string := L_FSM;
                 LPM_FILE: string ;
                 LPM_AVALUE: string := UNUSED;
                 LPM_TRUTHTYPE : string := FD;
                 LPM_HINT : string := UNUSED);
        port (DATA: in std_logic_vector(LPM_WIDTHIN-1 downto 0);
              CLOCK: in std_logic;
              ASET: in std_logic := '0';
              STATE: out std_logic_vector(LPM_WIDTHS-1 downto 0);
              RESULT: out std_logic_vector(LPM_WIDTHOUT-1 downto 0));
end component;

component LPM_AND
        generic (LPM_WIDTH : positive;
                 LPM_SIZE : positive;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_OR
        generic (LPM_WIDTH : positive;
                 LPM_SIZE : positive;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_XOR
        generic (LPM_WIDTH : positive;
                 LPM_SIZE : positive;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_MUX
        generic (LPM_WIDTH: positive;
                 LPM_WIDTHS : positive;
                 LPM_PIPELINE : integer := 0;
                 LPM_SIZE: positive;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
              ACLR : in std_logic := '0';
              CLOCK : in std_logic := '0';
              SEL : in std_logic_vector(LPM_WIDTHS-1 downto 0);
              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

end;

package body LPM_COMPONENTS is

    function str_to_int( s : string ) return integer is
    variable len : integer := s'length;
    variable ivalue : integer := 0;
    variable digit : integer;
    begin
    for i in len downto 1 loop
       case s(i) is
          when '0' =>
                digit := 0;
          when '1' =>
             digit := 1;
          when '2' =>
             digit := 2;
          when '3' =>
             digit := 3;
          when '4' =>
             digit := 4;
          when '5' =>
             digit := 5;
          when '6' =>
             digit := 6;
          when '7' =>
             digit := 7;
          when '8' =>
             digit := 8;
          when '9' =>
             digit := 9;
          when others =>
           ASSERT FALSE
           REPORT "Illegal Character "&  s(i) & "in string parameter! "
           SEVERITY ERROR;
   end case;
   ivalue := ivalue * 10 + digit;
   end loop;
   return ivalue;
 end;

end;