lpm_pack.vhd

《数字信号处理的FPGA实现》代码

------------------------------------------------------------------
-- LPM 210 Component Declaration Package  (Support string type generic)
------------------------------------------------------------------
-- Version 1.3   Date 07/30/97
------------------------------------------------------------------
-- Excluded:
--
-- 1. LPM_POLARITY.
-- 2. SCAN pins are eliminated from storage functions.
------------------------------------------------------------------
-- Assumptions:
--
--    LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,
--    LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE  default value is
--    string UNUSED.
------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

package LPM_COMPONENTS is

constant SIGNED : string := "SIGNED";
constant UNSIGNED : string := "UNSIGNED";
constant ADD : string := "ADD";
constant SUB : string := "SUB";
constant UP : string := "UP";
constant DOWN : string := "DOWN";
constant LOGICAL : string := "LOGICAL";
constant ROTATE : string := "ROTATE";
constant ARITHMETIC : string := "ARITHMETIC";
constant REGISTERED : string := "REGISTERED";
constant UNREGISTERED : string := "UNREGISTERED";
constant F : string := "F";
constant FD : string := "FD";
constant FR : string := "FR";
constant FDR : string := "FDR";
constant UNUSED : string := "UNUSED";
constant FFTYPE_DFF : string := "DFF";
constant FFTYPE_TFF : string := "TFF";
constant L_CONSTANT : string := "LPM_CONSTANT";
constant L_INV : string := "LPM_INV";
constant L_AND : string := "LPM_AND";
constant L_OR : string := "LPM_OR";
constant L_XOR : string := "LPM_XOR";
constant L_BUSTRI : string := "LPM_BUSTRI";
constant L_MUX : string := "LPM_MUX";
constant L_DECODE : string := "LPM_DECODE";
constant L_CLSHIFT : string := "LPM_CLSHIFT";
constant L_ADD_SUB : string := "LPM_ADD_SUB";
constant L_COMPARE : string := "LPM_COMPARE";
constant L_MULT : string := "LPM_MULT";
constant L_ABS : string := "LPM_ABS";
constant L_COUNTER : string := "LPM_COUNTER";
constant L_LATCH : string := "LPM_LATCH";
constant L_FF : string := "LPM_FF";
constant L_SHIFTREG : string := "LPM_SHIFTREG";
constant L_RAM_DQ : string := "LPM_RAM_DQ";
constant L_RAM_IO : string := "LPM_RAM_IO";
constant L_ROM : string := "LPM_ROM";
constant L_TTABLE : string := "LPM_TTABLE";
constant L_FSM : string := "LPM_FSM";
constant L_INPAD : string := "LPM_INPAD";
constant L_OUTPAD : string := "LPM_OUTPAD";
constant L_BIPAD : string := "LPM_BIPAD";
type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
function str_to_int(S : string) return integer;

component LPM_COUNTER
        generic (LPM_WIDTH : positive;
                 LPM_MODULUS: string := UNUSED;
                 LPM_AVALUE : string := UNUSED;
                 LPM_SVALUE : string := UNUSED;
                 LPM_DIRECTION : string := UNUSED;
                 LPM_TYPE: string := L_COUNTER;
                 LPM_PVALUE : string := UNUSED;
                 LPM_HINT : string := UNUSED);
        port (DATA: in std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS => '0');
              CLOCK : in std_logic ;
              CLK_EN : in std_logic := '1';
              CNT_EN : in std_logic := '1';
              UPDOWN : in std_logic := '1';
              SLOAD : in std_logic := '0';
              SSET : in std_logic := '0';
              SCLR : in std_logic := '0';
              ALOAD : in std_logic := '0';
              ASET : in std_logic := '0';
              ACLR : in std_logic := '0';
              EQ : out std_logic;
              Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_ABS
        generic (LPM_WIDTH : positive;
                 LPM_TYPE: string := L_ABS;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
              OVERFLOW: out std_logic);
end component;

component LPM_MULT
        generic (LPM_WIDTHA : positive;
                 LPM_WIDTHB : positive;
                 LPM_WIDTHS : positive;
                 LPM_WIDTHP : positive;
                 LPM_REPRESENTATION : string := UNSIGNED;
                 LPM_PIPELINE : integer := 0;
                 LPM_TYPE: string := L_MULT;
                 LPM_HINT : string := UNUSED);
        port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
              DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
              ACLR : in std_logic := '0';
              CLOCK : in std_logic := '1';
              SUM: in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
              RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end component;

component LPM_COMPARE
        generic (LPM_WIDTH : positive;
                 LPM_REPRESENTATION : string := SIGNED;
                 LPM_PIPELINE : integer := 0;
                 LPM_TYPE: string := L_COMPARE;
                 LPM_HINT : string := UNUSED);
        port (DATAA: in std_logic_vector(LPM_WIDTH-1 downto 0);
              DATAB: in std_logic_vector(LPM_WIDTH-1 downto 0);
              ACLR : in std_logic := '0';
              CLOCK : in std_logic := '1';
              AGB: out std_logic;
              AGEB: out std_logic;
              AEB: out std_logic;
              ANEB: out std_logic;
              ALB: out std_logic;
              ALEB: out std_logic);
end component;

component LPM_ADD_SUB
        generic (LPM_WIDTH: positive;
                 LPM_REPRESENTATION: string := SIGNED;
                 LPM_DIRECTION: string := UNUSED;
                 LPM_HINT : string := UNUSED;
                 LPM_PIPELINE : integer := 0;
                 LPM_TYPE: string := L_ADD_SUB);
        port (DATAA: in std_logic_vector(LPM_WIDTH-1 downto 0);
              DATAB: in std_logic_vector(LPM_WIDTH-1 downto 0);
              ACLR : in std_logic := '0';
              CLOCK : in std_logic := '1';
              CIN: in std_logic := '0';
              ADD_SUB: in std_logic := '1';
              RESULT: out std_logic_vector(LPM_WIDTH-1 downto 0);
              COUT: out std_logic;
              OVERFLOW: out std_logic);
end component;

component LPM_LATCH
        generic (LPM_WIDTH : positive;
                 LPM_PVALUE : string := UNUSED;
                 LPM_TYPE: string := L_LATCH;
                 LPM_AVALUE : string := UNUSED;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
              GATE : in std_logic;
              ASET : in std_logic := '0';
              ACLR : in std_logic := '0';
              Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_FF
        generic (LPM_WIDTH : positive;
                 LPM_AVALUE : string := UNUSED;
                 LPM_FFTYPE: string := FFTYPE_DFF;
                 LPM_TYPE: string := L_FF;
                 LPM_SVALUE : string := UNUSED);
                 --LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
              CLOCK : in std_logic;
              ENABLE : in std_logic := '1';
              SLOAD : in std_logic := '0';
              SCLR : in std_logic := '0';
              SSET : in std_logic := '0';
              ALOAD : in std_logic := '0';
              ACLR : in std_logic := '0';
              ASET : in std_logic := '0';
              Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

component LPM_SHIFTREG
        generic (LPM_WIDTH : positive;
                 LPM_AVALUE : string := UNUSED;
                 LPM_DIRECTION: string := UNUSED;
                 LPM_TYPE: string := L_SHIFTREG;
                 LPM_SVALUE : string := UNUSED;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0) := (OTHERS => '0');
              CLOCK : in std_logic;
              ENABLE : in std_logic := '1';
              SHIFTIN : in std_logic := '1';
              LOAD : in std_logic := '0';
              SCLR : in std_logic := '0';
              SSET : in std_logic := '0';
              ACLR : in std_logic := '0';
              ASET : in std_logic := '0';
              Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
              SHIFTOUT : out std_logic);
end component;

component LPM_DECODE
        generic (LPM_WIDTH : positive;
                 LPM_TYPE: string := L_DECODE;
                 LPM_PIPELINE : integer := 0;
                 LPM_DECODES : natural;
                 LPM_HINT : string := UNUSED);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
              CLOCK : in std_logic := '1';
              ACLR : in std_logic := '0';
              ENABLE : in std_logic := '1';
              EQ : out std_logic_vector(LPM_DECODES-1 downto 0));
end component;

component LPM_CONSTANT
        generic (LPM_WIDTH : positive;
                 LPM_CVALUE: natural;
                 LPM_TYPE: string := L_CONSTANT;
                 LPM_STRENGTH : string := UNUSED;