210model.v

《数字信号处理的FPGA实现》代码

    assign q = tmp_q;
endmodule // lpm_ff
 
module lpm_inpad ( result, pad ) ;

  parameter lpm_type = "lpm_inpad" ;
  parameter lpm_width = 1 ;

  input  [lpm_width-1:0] pad ;
  output [lpm_width-1:0] result ;

  reg    [lpm_width-1:0] result ;

  always @(pad)
    begin
      result = pad ;
    end

endmodule // lpm_inpad

module lpm_inv ( result, data ) ;

  parameter lpm_type = "lpm_inv" ;
  parameter lpm_width = 1 ;

  input  [lpm_width-1:0] data ;
  output [lpm_width-1:0] result ;

  reg    [lpm_width-1:0] result ;

  always @(data)
    begin
      result = ~data ;
    end

endmodule // lpm_inv

module lpm_latch ( q, data, gate, aset, aclr );

  parameter lpm_type = "lpm_latch" ;
  parameter lpm_width = 1 ;
  parameter lpm_avalue = "UNUSED" ;
  parameter lpm_pvalue = "UNUSED" ;

  input  [lpm_width-1:0] data ;
  input  gate, aset, aclr ;
  output [lpm_width-1:0] q ;

  reg [lpm_width-1:0] q ;

//---------------------------------------------------------------//
//  function integer str_to_int ;
//---------------------------------------------------------------//
  function integer str_to_int ;
    input  [8*16:1] s; 
    reg [8*16:1] reg_s;
    reg [8:1]   digit ;
    reg [8:1] tmp;
    integer   m , ivalue ; 
    begin 
  
	ivalue = 0;
	reg_s = s;
        for (m=1; m<=16; m= m+1 ) 
        begin 
		tmp = reg_s[128:121];
		digit = tmp & 8'b00001111;
		reg_s = reg_s << 8;	
                ivalue = ivalue * 10 + digit; 
        end
	str_to_int = ivalue;
    end
  endfunction
//---------------------------------------------------------------//

  always @(data or gate or aclr or aset)
    begin
	if (aclr)
		q = 'b0;
	else if (aset)
	    begin
		if (lpm_avalue == "UNUSED")
			q = {lpm_width{1'b1}};
		else	
			q = str_to_int(lpm_avalue);
	    end
	else if (gate)
		q = data;
	
    end

endmodule // lpm_latch

module lpm_mult ( result, dataa, datab, sum, clock, aclr ) ;

  parameter lpm_type       = "lpm_mult" ;
  parameter lpm_widtha     = 1 ;
  parameter lpm_widthb     = 1 ;
  parameter lpm_widths     = 1 ;
  parameter lpm_widthp     = 2 ;
  parameter lpm_pipeline   = 0 ;
  parameter lpm_representation  = "UNSIGNED" ;

  input  clock ;
  input  aclr ;
  input  [lpm_widtha-1:0] dataa ;
  input  [lpm_widthb-1:0] datab ;
  input  [lpm_widths-1:0] sum ;
  output [lpm_widthp-1:0] result;

  // inernal reg
  reg   [lpm_widthp-1:0] tmp_result ;
  reg   [lpm_widthp-1:0] tmp_result2 [lpm_pipeline:0];
  reg   [lpm_widtha-2:0] a_int ;
  reg   [lpm_widthb-2:0] b_int ;
  reg   [lpm_widths-2:0] s_int ;
  reg   [lpm_widthp-2:0] p_reg ;
  integer p_int;
  integer i, j, k, m, n, p, maxs_mn ;
  integer int_dataa, int_datab, int_sum, int_result ;


  always @( dataa or datab or sum)
    begin
      		if (lpm_representation == "UNSIGNED")
        		begin
		  			int_dataa = dataa ;
		  			int_datab = datab ;
		  			int_sum = sum ;
        		end
      		else 
  		if (lpm_representation == "SIGNED")
          		begin
		  		// convert signed dataa
          		if(dataa[lpm_widtha-1] == 1)
          		begin
            		int_dataa = 0 ;
            		for(i = 0; i < lpm_widtha - 1; i = i + 1)
                		a_int[i] = dataa[i] ^ 1;
            		int_dataa = (a_int + 1) * (-1) ;
          		end
          		else int_dataa = dataa ;

		  		// convert signed datab
          		if(datab[lpm_widthb-1] == 1)
          		begin
            		int_datab = 0 ;
            		for(j = 0; j < lpm_widthb - 1; j = j + 1)
                		b_int[j] = datab[j] ^ 1;
            		int_datab = (b_int + 1) * (-1) ;
          		end
          		else int_datab = datab ;

		  		// convert signed sum
          		if(sum[lpm_widths-1] == 1)
          		begin
            		int_sum = 0 ;
            		for(k = 0; k < lpm_widths - 1; k = k + 1)
                		s_int[k] = sum[k] ^ 1;
            		int_sum = (s_int + 1) * (-1) ;
          		end
          		else int_sum = sum ;
				end
        		else 
          		begin
  		  			int_dataa = {lpm_widtha{1'bx}} ;
  		  			int_datab = {lpm_widthb{1'bx}} ;
  		  			int_sum   = {lpm_widths{1'bx}} ;
          		end

	  		p_int = int_dataa * int_datab + int_sum ;
			maxs_mn = ((lpm_widtha+lpm_widthb)>lpm_widths)?lpm_widtha+lpm_widthb:lpm_widths ;
	  		if(lpm_widthp >= maxs_mn)
				tmp_result = p_int ;
	  		else
				begin
					p_reg = p_int;
					for(m = 0; m < lpm_widthp; m = m +1)
						tmp_result[lpm_widthp-1-m] = p_reg[maxs_mn-1-m] ;
				end	
	end

	always @(posedge clock or posedge aclr)
	begin
	  if(aclr)
		begin
			for(p = 0; p <= lpm_pipeline; p = p + 1)
				tmp_result2[p] = 'b0;
		end
	  else
	  begin :syn_block
	  	tmp_result2[lpm_pipeline] = tmp_result ;
		for(n = 0; n < lpm_pipeline; n = n +1)
			tmp_result2[n] = tmp_result2[n+1] ;
	  end
	end

  assign result = (lpm_pipeline > 0) ? tmp_result2[0] : tmp_result ;

 endmodule // lpm_mult

module lpm_mux ( result, clock, data, aclr, sel ) ;

  parameter lpm_type = "lpm_mux" ;
  parameter lpm_width =1 ;
  parameter lpm_size =1 ;
  parameter lpm_widths = 1;
  parameter lpm_pipeline = 0;

  input  [(lpm_size * lpm_width)-1:0] data;
  input aclr;
  input clock;
  input [lpm_widths-1:0] sel;
  output [lpm_width-1:0] result ;

  integer i, j, m, n;
  reg 	[lpm_width-1:0] tmp_result;
  reg	[lpm_width-1:0] tmp_result2 [lpm_pipeline:0];

  always @(data or sel)
    begin
	tmp_result = 0;
	for (m=0; m<lpm_width; m=m+1)
	begin
		n = sel * lpm_width + m;
		tmp_result[m] = data[n];
	end
    end

    always @(posedge clock or posedge aclr)
    begin
        if (aclr)
            begin
                for(i = 0; i <= lpm_pipeline; i = i + 1)
                        tmp_result2[i] = 'b0 ;
            end
        else
        begin
        	tmp_result2[lpm_pipeline] = tmp_result ;
        	for(j = 0; j < lpm_pipeline; j = j +1)
            		tmp_result2[j] = tmp_result2[j+1] ;
        end
      end

  assign result = (lpm_pipeline > 0) ? tmp_result2[0] : tmp_result;
endmodule // lpm_mux

module lpm_or ( result, data ) ;

  parameter lpm_type = "lpm_and" ;
  parameter lpm_width = 1 ;
  parameter lpm_size = 1 ;

  input  [(lpm_size * lpm_width)-1:0] data;
  output [lpm_width-1:0] result ;

  reg    [lpm_width-1:0] result ;
  integer i, j, k;

  always @(data)
    begin
	for ( i=0; i<lpm_width; i=i+1)
	begin
		result[i] = data[i];
		for ( j=1; j<lpm_size; j=j+1)
		begin
			k = j * lpm_width + i;
			result[i] = result[i] | data[k];
		end
	end
    end

endmodule // lpm_and

module lpm_outpad ( data, pad ) ;

  parameter lpm_type = "lpm_outpad" ;
  parameter lpm_width = 1 ;

  input [lpm_width-1:0] data ;
  output  [lpm_width-1:0] pad ;

  reg   [lpm_width-1:0] pad ;

  always @(data)
    begin
      pad = data ;
    end

endmodule // lpm_outpad

module lpm_shiftreg ( q, shiftout,
        data, clock, enable,
        aclr, aset, 
        sclr, sset,
        shiftin, load) ;

  parameter lpm_type = "lpm_shiftreg" ;
  parameter lpm_width  = 1 ;
  parameter lpm_avalue = "UNUSED" ;
  parameter lpm_svalue = "UNUSED" ;
  parameter lpm_direction = "LEFT" ;

  input  [lpm_width-1:0] data ;
  input  clock, enable ;
  input  aclr, aset;
  input  sclr, sset ;
  input  shiftin, load ;
  output [lpm_width-1:0] q;
  output shiftout ;

  reg   [lpm_width-1:0] tmp_q ;
  reg   abit ;
  integer i ;

  wire  tmp_shiftout;

//---------------------------------------------------------------//
//  function integer str_to_int ;
//---------------------------------------------------------------//
  function integer str_to_int ;
    input  [8*16:1] s; 
    reg [8*16:1] reg_s;
    reg [8:1]   digit ;
    reg [8:1] tmp;
    integer   m , ivalue ; 
    begin 
  
	ivalue = 0;
	reg_s = s;
        for (m=1; m<=16; m= m+1 ) 
        begin 
		tmp = reg_s[128:121];
		digit = tmp & 8'b00001111;
		reg_s = reg_s << 8;	
                ivalue = ivalue * 10 + digit; 
        end
	str_to_int = ivalue;
    end
  endfunction
//---------------------------------------------------------------//

  always @( posedge clock or posedge aclr or posedge aset )
    begin :asyn_block // Asynchronous process

	if (aclr)
	    begin
        	 tmp_q = 0 ;
	    end
	else if (aset )
	    begin
		if (lpm_avalue === "UNUSED")
                        tmp_q = {lpm_width{1'b1}};
		else
         	 	tmp_q = str_to_int(lpm_avalue) ;
	    end
	else

    begin :syn_block // Synchronous process
      	if (enable)
	  begin
		if(sclr)
		  begin
       			tmp_q = 0;
		  end
      		else if (sset)
		  begin
			if (lpm_svalue === "UNUSED")
				tmp_q = {lpm_width{1'b1}};
			else
         	 		tmp_q = str_to_int(lpm_svalue) ;
		  end
      		else if (load)  
		  begin
        		tmp_q = data ;
		  end
      		else if (!load)
       		  begin
  			if(lpm_direction === "LEFT")
  				begin
					{abit,tmp_q} = {tmp_q,shiftin};
  				end
  			else if(lpm_direction === "RIGHT")
  				begin
  					{tmp_q,abit} = {shiftin,tmp_q};
  				end
        	  end
	  end
    end
  end


   assign tmp_shiftout = (lpm_direction === "LEFT")?tmp_q[lpm_width-1]:tmp_q[0];
   assign q = tmp_q ;
   assign shiftout = tmp_shiftout ;

endmodule // lpm_shiftreg
 
module lpm_xor ( result, data ) ;

  parameter lpm_type = "lpm_and" ;
  parameter lpm_width = 1 ;
  parameter lpm_size = 1 ;

  input  [(lpm_size * lpm_width)-1:0] data;
  output [lpm_width-1:0] result ;

  reg    [lpm_width-1:0] result ;
  integer i, j, k;

  always @(data)
    begin
	for ( i=0; i<lpm_width; i=i+1)
	begin
		result[i] = data[i];
		for ( j=1; j<lpm_size; j=j+1)
		begin
			k = j * lpm_width + i;
			result[i] = result[i] ^ data[k];
		end
	end
    end

endmodule // lpm_and