mti_v.csh

《数字信号处理的FPGA实现》代码

#!/bin/csh -f
#---------------------------------------------------------- 
# Model Technology Incorporated Verilog compiler script for
# the book: Digital Signal Processing with FPGAs
# Author-EMAIL: [e-mail]
#---------------------------------------------------------- 
if ( ! -r convert_hex2ver.sl ) then
  echo "ERROR: Could not find convert_hex2ver.sl"
  echo "Compile the shared objects with"
  echo -n "gcc -c -I/<install_dir>/modeltech/include" 
  echo  " convert_hex2ver.c" 
  echo -n "ld -G -B symbolic -o convert_hex2ver.sl"
  echo " convert_hex2ver.o"
endif

if ( ! -d lpm ) then
  vlib lpm 
  echo "Library directory lpm created."
else
  echo "Library directory lpm found."
endif

echo Compile lpm package.
vlog -work lpm -quiet 220model.v

echo Compile chapter 1 entitys. 
vlog -work lpm -quiet example.v
vlog -work lpm -quiet fun_text.v

echo Compile chapter 2 components.
vlog -work lpm -quiet csa7.v csa7cin.v
vlog -work lpm -quiet add_ff8.v add_ff8cin.v
echo Compile chapter 2 entitys. 
vlog -work lpm -quiet add_1p.v add_2p.v add_3p.v
vlog -work lpm -quiet mul_ser.v cordic.v 

echo Compile chapter 3 components. 
vlog -work lpm -quiet case3.v case5p.v case3s.v
echo Compile chapter 3 entitys.
vlog -work lpm -quiet fir_gen.v fir_srg.v dafsm.v
vlog -work lpm -quiet darom.v dasign.v dapara.v 

echo Compile chapter 4 entitys.
vlog -work lpm -quiet iir.v iir_pipe.v iir_par.v  

echo Compile chapter 5 entitys.
vlog -work lpm -quiet cic3r32.v cic3s32.v
vlog -work lpm -quiet db4poly.v db4latti.v  

echo Compile chapter 6 entitys.
vlog -work lpm -quiet rader7.v ccmul.v bfproc.v

echo Compile chapter 7 entitys.
vlog -work lpm -quiet lfsr.v lfsr6s3.v ammod.v  

echo Compile 2. edition entitys.
vlog -work lpm -quiet div_res.v div_aegp.v 
vlog -work lpm -quiet fir_lms.v fir6dlms.v