mgc6h1.hier_info

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

|mgc6h1
data[0] => data[0]~11.IN1
data[1] => data[1]~10.IN1
data[2] => data[2]~9.IN1
data[3] => data[3]~8.IN1
data[4] => data[4]~7.IN1
data[5] => data[5]~6.IN1
data[6] => data[6]~5.IN1
data[7] => data[7]~4.IN1
data[8] => data[8]~3.IN1
data[9] => data[9]~2.IN1
data[10] => data[10]~1.IN1
data[11] => data[11]~0.IN1
inclock => inclock~0.IN1
outclock => outclock~0.IN1
qa[0] <= alt3pram:mgl_prim1.qa
qa[1] <= alt3pram:mgl_prim1.qa
qa[2] <= alt3pram:mgl_prim1.qa
qa[3] <= alt3pram:mgl_prim1.qa
qa[4] <= alt3pram:mgl_prim1.qa
qa[5] <= alt3pram:mgl_prim1.qa
qa[6] <= alt3pram:mgl_prim1.qa
qa[7] <= alt3pram:mgl_prim1.qa
qa[8] <= alt3pram:mgl_prim1.qa
qa[9] <= alt3pram:mgl_prim1.qa
qa[10] <= alt3pram:mgl_prim1.qa
qa[11] <= alt3pram:mgl_prim1.qa
qb[0] <= alt3pram:mgl_prim1.qb
qb[1] <= alt3pram:mgl_prim1.qb
qb[2] <= alt3pram:mgl_prim1.qb
qb[3] <= alt3pram:mgl_prim1.qb
qb[4] <= alt3pram:mgl_prim1.qb
qb[5] <= alt3pram:mgl_prim1.qb
qb[6] <= alt3pram:mgl_prim1.qb
qb[7] <= alt3pram:mgl_prim1.qb
qb[8] <= alt3pram:mgl_prim1.qb
qb[9] <= alt3pram:mgl_prim1.qb
qb[10] <= alt3pram:mgl_prim1.qb
qb[11] <= alt3pram:mgl_prim1.qb
rdaddress_a[0] => rdaddress_a[0]~9.IN1
rdaddress_a[1] => rdaddress_a[1]~8.IN1
rdaddress_a[2] => rdaddress_a[2]~7.IN1
rdaddress_a[3] => rdaddress_a[3]~6.IN1
rdaddress_a[4] => rdaddress_a[4]~5.IN1
rdaddress_a[5] => rdaddress_a[5]~4.IN1
rdaddress_a[6] => rdaddress_a[6]~3.IN1
rdaddress_a[7] => rdaddress_a[7]~2.IN1
rdaddress_a[8] => rdaddress_a[8]~1.IN1
rdaddress_a[9] => rdaddress_a[9]~0.IN1
rdaddress_b[0] => rdaddress_b[0]~9.IN1
rdaddress_b[1] => rdaddress_b[1]~8.IN1
rdaddress_b[2] => rdaddress_b[2]~7.IN1
rdaddress_b[3] => rdaddress_b[3]~6.IN1
rdaddress_b[4] => rdaddress_b[4]~5.IN1
rdaddress_b[5] => rdaddress_b[5]~4.IN1
rdaddress_b[6] => rdaddress_b[6]~3.IN1
rdaddress_b[7] => rdaddress_b[7]~2.IN1
rdaddress_b[8] => rdaddress_b[8]~1.IN1
rdaddress_b[9] => rdaddress_b[9]~0.IN1
wraddress[0] => wraddress[0]~9.IN1
wraddress[1] => wraddress[1]~8.IN1
wraddress[2] => wraddress[2]~7.IN1
wraddress[3] => wraddress[3]~6.IN1
wraddress[4] => wraddress[4]~5.IN1
wraddress[5] => wraddress[5]~4.IN1
wraddress[6] => wraddress[6]~3.IN1
wraddress[7] => wraddress[7]~2.IN1
wraddress[8] => wraddress[8]~1.IN1
wraddress[9] => wraddress[9]~0.IN1
wren => wren~0.IN1


|mgc6h1|alt3pram:mgl_prim1
wren => altdpram:altdpram_component1.wren
wren => altdpram:altdpram_component2.wren
data[0] => altdpram:altdpram_component1.data[0]
data[0] => altdpram:altdpram_component2.data[0]
data[1] => altdpram:altdpram_component1.data[1]
data[1] => altdpram:altdpram_component2.data[1]
data[2] => altdpram:altdpram_component1.data[2]
data[2] => altdpram:altdpram_component2.data[2]
data[3] => altdpram:altdpram_component1.data[3]
data[3] => altdpram:altdpram_component2.data[3]
data[4] => altdpram:altdpram_component1.data[4]
data[4] => altdpram:altdpram_component2.data[4]
data[5] => altdpram:altdpram_component1.data[5]
data[5] => altdpram:altdpram_component2.data[5]
data[6] => altdpram:altdpram_component1.data[6]
data[6] => altdpram:altdpram_component2.data[6]
data[7] => altdpram:altdpram_component1.data[7]
data[7] => altdpram:altdpram_component2.data[7]
data[8] => altdpram:altdpram_component1.data[8]
data[8] => altdpram:altdpram_component2.data[8]
data[9] => altdpram:altdpram_component1.data[9]
data[9] => altdpram:altdpram_component2.data[9]
data[10] => altdpram:altdpram_component1.data[10]
data[10] => altdpram:altdpram_component2.data[10]
data[11] => altdpram:altdpram_component1.data[11]
data[11] => altdpram:altdpram_component2.data[11]
wraddress[0] => altdpram:altdpram_component1.wraddress[0]
wraddress[0] => altdpram:altdpram_component2.wraddress[0]
wraddress[1] => altdpram:altdpram_component1.wraddress[1]
wraddress[1] => altdpram:altdpram_component2.wraddress[1]
wraddress[2] => altdpram:altdpram_component1.wraddress[2]
wraddress[2] => altdpram:altdpram_component2.wraddress[2]
wraddress[3] => altdpram:altdpram_component1.wraddress[3]
wraddress[3] => altdpram:altdpram_component2.wraddress[3]
wraddress[4] => altdpram:altdpram_component1.wraddress[4]
wraddress[4] => altdpram:altdpram_component2.wraddress[4]
wraddress[5] => altdpram:altdpram_component1.wraddress[5]
wraddress[5] => altdpram:altdpram_component2.wraddress[5]
wraddress[6] => altdpram:altdpram_component1.wraddress[6]
wraddress[6] => altdpram:altdpram_component2.wraddress[6]
wraddress[7] => altdpram:altdpram_component1.wraddress[7]
wraddress[7] => altdpram:altdpram_component2.wraddress[7]
wraddress[8] => altdpram:altdpram_component1.wraddress[8]
wraddress[8] => altdpram:altdpram_component2.wraddress[8]
wraddress[9] => altdpram:altdpram_component1.wraddress[9]
wraddress[9] => altdpram:altdpram_component2.wraddress[9]
inclock => altdpram:altdpram_component1.inclock
inclock => altdpram:altdpram_component2.inclock
inclocken => ~NO_FANOUT~
outclock => altdpram:altdpram_component1.outclock
outclock => altdpram:altdpram_component2.outclock
outclocken => ~NO_FANOUT~
aclr => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
rdaddress_a[0] => altdpram:altdpram_component1.rdaddress[0]
rdaddress_a[1] => altdpram:altdpram_component1.rdaddress[1]
rdaddress_a[2] => altdpram:altdpram_component1.rdaddress[2]
rdaddress_a[3] => altdpram:altdpram_component1.rdaddress[3]
rdaddress_a[4] => altdpram:altdpram_component1.rdaddress[4]
rdaddress_a[5] => altdpram:altdpram_component1.rdaddress[5]
rdaddress_a[6] => altdpram:altdpram_component1.rdaddress[6]
rdaddress_a[7] => altdpram:altdpram_component1.rdaddress[7]
rdaddress_a[8] => altdpram:altdpram_component1.rdaddress[8]
rdaddress_a[9] => altdpram:altdpram_component1.rdaddress[9]
rdaddress_b[0] => altdpram:altdpram_component2.rdaddress[0]
rdaddress_b[1] => altdpram:altdpram_component2.rdaddress[1]
rdaddress_b[2] => altdpram:altdpram_component2.rdaddress[2]
rdaddress_b[3] => altdpram:altdpram_component2.rdaddress[3]
rdaddress_b[4] => altdpram:altdpram_component2.rdaddress[4]
rdaddress_b[5] => altdpram:altdpram_component2.rdaddress[5]
rdaddress_b[6] => altdpram:altdpram_component2.rdaddress[6]
rdaddress_b[7] => altdpram:altdpram_component2.rdaddress[7]
rdaddress_b[8] => altdpram:altdpram_component2.rdaddress[8]
rdaddress_b[9] => altdpram:altdpram_component2.rdaddress[9]
qa[0] <= altdpram:altdpram_component1.q[0]
qa[1] <= altdpram:altdpram_component1.q[1]
qa[2] <= altdpram:altdpram_component1.q[2]
qa[3] <= altdpram:altdpram_component1.q[3]
qa[4] <= altdpram:altdpram_component1.q[4]
qa[5] <= altdpram:altdpram_component1.q[5]
qa[6] <= altdpram:altdpram_component1.q[6]
qa[7] <= altdpram:altdpram_component1.q[7]
qa[8] <= altdpram:altdpram_component1.q[8]
qa[9] <= altdpram:altdpram_component1.q[9]
qa[10] <= altdpram:altdpram_component1.q[10]
qa[11] <= altdpram:altdpram_component1.q[11]
qb[0] <= altdpram:altdpram_component2.q[0]
qb[1] <= altdpram:altdpram_component2.q[1]
qb[2] <= altdpram:altdpram_component2.q[2]
qb[3] <= altdpram:altdpram_component2.q[3]
qb[4] <= altdpram:altdpram_component2.q[4]
qb[5] <= altdpram:altdpram_component2.q[5]
qb[6] <= altdpram:altdpram_component2.q[6]
qb[7] <= altdpram:altdpram_component2.q[7]
qb[8] <= altdpram:altdpram_component2.q[8]
qb[9] <= altdpram:altdpram_component2.q[9]
qb[10] <= altdpram:altdpram_component2.q[10]
qb[11] <= altdpram:altdpram_component2.q[11]


|mgc6h1|alt3pram:mgl_prim1|altdpram:altdpram_component1
wren => altsyncram:ram_block.wren_a
data[0] => altsyncram:ram_block.data_a[0]
data[1] => altsyncram:ram_block.data_a[1]
data[2] => altsyncram:ram_block.data_a[2]
data[3] => altsyncram:ram_block.data_a[3]
data[4] => altsyncram:ram_block.data_a[4]
data[5] => altsyncram:ram_block.data_a[5]
data[6] => altsyncram:ram_block.data_a[6]
data[7] => altsyncram:ram_block.data_a[7]
data[8] => altsyncram:ram_block.data_a[8]
data[9] => altsyncram:ram_block.data_a[9]
data[10] => altsyncram:ram_block.data_a[10]
data[11] => altsyncram:ram_block.data_a[11]
wraddress[0] => altsyncram:ram_block.address_a[0]
wraddress[1] => altsyncram:ram_block.address_a[1]
wraddress[2] => altsyncram:ram_block.address_a[2]
wraddress[3] => altsyncram:ram_block.address_a[3]
wraddress[4] => altsyncram:ram_block.address_a[4]
wraddress[5] => altsyncram:ram_block.address_a[5]
wraddress[6] => altsyncram:ram_block.address_a[6]
wraddress[7] => altsyncram:ram_block.address_a[7]
wraddress[8] => altsyncram:ram_block.address_a[8]
wraddress[9] => altsyncram:ram_block.address_a[9]
inclock => altsyncram:ram_block.clock0
inclocken => ~NO_FANOUT~
rden => ~NO_FANOUT~
rdaddress[0] => altsyncram:ram_block.address_b[0]
rdaddress[1] => altsyncram:ram_block.address_b[1]
rdaddress[2] => altsyncram:ram_block.address_b[2]
rdaddress[3] => altsyncram:ram_block.address_b[3]
rdaddress[4] => altsyncram:ram_block.address_b[4]
rdaddress[5] => altsyncram:ram_block.address_b[5]
rdaddress[6] => altsyncram:ram_block.address_b[6]
rdaddress[7] => altsyncram:ram_block.address_b[7]
rdaddress[8] => altsyncram:ram_block.address_b[8]
rdaddress[9] => altsyncram:ram_block.address_b[9]
outclock => altsyncram:ram_block.clock1
outclocken => ~NO_FANOUT~
aclr => ~NO_FANOUT~
byteena[0] => ~NO_FANOUT~
wraddressstall => ~NO_FANOUT~
rdaddressstall => ~NO_FANOUT~
q[0] <= altsyncram:ram_block.q_b[0]
q[1] <= altsyncram:ram_block.q_b[1]
q[2] <= altsyncram:ram_block.q_b[2]
q[3] <= altsyncram:ram_block.q_b[3]
q[4] <= altsyncram:ram_block.q_b[4]
q[5] <= altsyncram:ram_block.q_b[5]
q[6] <= altsyncram:ram_block.q_b[6]
q[7] <= altsyncram:ram_block.q_b[7]
q[8] <= altsyncram:ram_block.q_b[8]
q[9] <= altsyncram:ram_block.q_b[9]
q[10] <= altsyncram:ram_block.q_b[10]
q[11] <= altsyncram:ram_block.q_b[11]


|mgc6h1|alt3pram:mgl_prim1|altdpram:altdpram_component1|altsyncram:ram_block
wren_a => altsyncram_voo1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_voo1:auto_generated.data_a[0]
data_a[1] => altsyncram_voo1:auto_generated.data_a[1]
data_a[2] => altsyncram_voo1:auto_generated.data_a[2]
data_a[3] => altsyncram_voo1:auto_generated.data_a[3]
data_a[4] => altsyncram_voo1:auto_generated.data_a[4]
data_a[5] => altsyncram_voo1:auto_generated.data_a[5]
data_a[6] => altsyncram_voo1:auto_generated.data_a[6]
data_a[7] => altsyncram_voo1:auto_generated.data_a[7]
data_a[8] => altsyncram_voo1:auto_generated.data_a[8]
data_a[9] => altsyncram_voo1:auto_generated.data_a[9]
data_a[10] => altsyncram_voo1:auto_generated.data_a[10]
data_a[11] => altsyncram_voo1:auto_generated.data_a[11]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
address_a[0] => altsyncram_voo1:auto_generated.address_a[0]
address_a[1] => altsyncram_voo1:auto_generated.address_a[1]
address_a[2] => altsyncram_voo1:auto_generated.address_a[2]
address_a[3] => altsyncram_voo1:auto_generated.address_a[3]
address_a[4] => altsyncram_voo1:auto_generated.address_a[4]
address_a[5] => altsyncram_voo1:auto_generated.address_a[5]
address_a[6] => altsyncram_voo1:auto_generated.address_a[6]
address_a[7] => altsyncram_voo1:auto_generated.address_a[7]
address_a[8] => altsyncram_voo1:auto_generated.address_a[8]
address_a[9] => altsyncram_voo1:auto_generated.address_a[9]
address_b[0] => altsyncram_voo1:auto_generated.address_b[0]
address_b[1] => altsyncram_voo1:auto_generated.address_b[1]
address_b[2] => altsyncram_voo1:auto_generated.address_b[2]
address_b[3] => altsyncram_voo1:auto_generated.address_b[3]
address_b[4] => altsyncram_voo1:auto_generated.address_b[4]
address_b[5] => altsyncram_voo1:auto_generated.address_b[5]
address_b[6] => altsyncram_voo1:auto_generated.address_b[6]
address_b[7] => altsyncram_voo1:auto_generated.address_b[7]
address_b[8] => altsyncram_voo1:auto_generated.address_b[8]
address_b[9] => altsyncram_voo1:auto_generated.address_b[9]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_voo1:auto_generated.clock0
clock1 => altsyncram_voo1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_a[8] <= <GND>
q_a[9] <= <GND>
q_a[10] <= <GND>
q_a[11] <= <GND>
q_b[0] <= altsyncram_voo1:auto_generated.q_b[0]
q_b[1] <= altsyncram_voo1:auto_generated.q_b[1]
q_b[2] <= altsyncram_voo1:auto_generated.q_b[2]
q_b[3] <= altsyncram_voo1:auto_generated.q_b[3]
q_b[4] <= altsyncram_voo1:auto_generated.q_b[4]
q_b[5] <= altsyncram_voo1:auto_generated.q_b[5]
q_b[6] <= altsyncram_voo1:auto_generated.q_b[6]
q_b[7] <= altsyncram_voo1:auto_generated.q_b[7]
q_b[8] <= altsyncram_voo1:auto_generated.q_b[8]
q_b[9] <= altsyncram_voo1:auto_generated.q_b[9]
q_b[10] <= altsyncram_voo1:auto_generated.q_b[10]
q_b[11] <= altsyncram_voo1:auto_generated.q_b[11]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|mgc6h1|alt3pram:mgl_prim1|altdpram:altdpram_component1|altsyncram:ram_block|altsyncram_voo1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3