prev_cmp_ffti.fit.qmsg

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.328 ns register register " "Info: Estimated most critical path is register to register delay of 8.328 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:11:Pipe\|Yo\[15\] 1 REG LAB_X21_Y2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y2; Fanout = 2; REG Node = 'cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:11:Pipe\|Yo\[15\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:11:Pipe|Yo[15] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "I:/fftinterface/p2r_CordicPipe.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.253 ns) + CELL(0.114 ns) 3.367 ns cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Add0~303 2 COMB LAB_X8_Y12 30 " "Info: 2: + IC(3.253 ns) + CELL(0.114 ns) = 3.367 ns; Loc. = LAB_X8_Y12; Fanout = 30; COMB Node = 'cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Add0~303'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.367 ns" { cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:11:Pipe|Yo[15] cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Add0~303 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.990 ns) + CELL(0.575 ns) 6.932 ns cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[7\]~90COUT1 3 COMB LAB_X18_Y3 2 " "Info: 3: + IC(2.990 ns) + CELL(0.575 ns) = 6.932 ns; Loc. = LAB_X18_Y3; Fanout = 2; COMB Node = 'cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[7\]~90COUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.565 ns" { cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Add0~303 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[7]~90COUT1 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "I:/fftinterface/p2r_CordicPipe.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 7.012 ns cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[8\]~89COUT1 4 COMB LAB_X18_Y3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 7.012 ns; Loc. = LAB_X18_Y3; Fanout = 2; COMB Node = 'cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[8\]~89COUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[7]~90COUT1 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[8]~89COUT1 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "I:/fftinterface/p2r_CordicPipe.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 7.092 ns cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[9\]~88COUT1 5 COMB LAB_X18_Y3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 7.092 ns; Loc. = LAB_X18_Y3; Fanout = 2; COMB Node = 'cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[9\]~88COUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[8]~89COUT1 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[9]~88COUT1 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "I:/fftinterface/p2r_CordicPipe.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 7.172 ns cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[10\]~87COUT1 6 COMB LAB_X18_Y3 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 7.172 ns; Loc. = LAB_X18_Y3; Fanout = 2; COMB Node = 'cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[10\]~87COUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[9]~88COUT1 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[10]~87COUT1 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "I:/fftinterface/p2r_CordicPipe.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 7.430 ns cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[11\]~86 7 COMB LAB_X18_Y3 4 " "Info: 7: + IC(0.000 ns) + CELL(0.258 ns) = 7.430 ns; Loc. = LAB_X18_Y3; Fanout = 4; COMB Node = 'cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[11\]~86'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[10]~87COUT1 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[11]~86 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "I:/fftinterface/p2r_CordicPipe.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 8.328 ns cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[15\] 8 REG LAB_X18_Y3 5 " "Info: 8: + IC(0.000 ns) + CELL(0.898 ns) = 8.328 ns; Loc. = LAB_X18_Y3; Fanout = 5; REG Node = 'cfft1024X12:inst1\|cfft:aCfft\|mulfactor:amulfactor\|sc_corproc:u1\|p2r_cordic:u1\|p2r_CordicPipe:\\gen_pipe:12:Pipe\|Xo\[15\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.898 ns" { cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[11]~86 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[15] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "I:/fftinterface/p2r_CordicPipe.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.085 ns ( 25.04 % ) " "Info: Total cell delay = 2.085 ns ( 25.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.243 ns ( 74.96 % ) " "Info: Total interconnect delay = 6.243 ns ( 74.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.328 ns" { cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:11:Pipe|Yo[15] cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Add0~303 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[7]~90COUT1 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[8]~89COUT1 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[9]~88COUT1 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[10]~87COUT1 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[11]~86 cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor|sc_corproc:u1|p2r_cordic:u1|p2r_CordicPipe:\gen_pipe:12:Pipe|Xo[15] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 22 " "Info: Average interconnect usage is 20% of the available device resources. Peak interconnect usage is 22%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X14_Y0 X27_Y14 " "Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Info: Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_MAIN_TITLE" "8 " "Info: Fitter merged 8 physical RAM blocks that contain multiple logical RAM block slices into a single location" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_TITLE" "" "Info: Following physical RAM blocks contain multiple logical RAM block slices" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M4K_X13_Y9 " "Info: Physical RAM block M4K_X13_Y9 contains the following RAM block slices" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a7 " "Info: RAM block slice \"ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a7\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a7 " "Info: RAM block slice \"ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a7\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a6 " "Info: RAM block slice \"ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a6\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a6 " "Info: RAM block slice \"ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a6\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0}  } {  } 2 0 "Physical RAM block %1!s! contains the following RAM block slices" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M4K_X13_Y11 " "Info: Physical RAM block M4K_X13_Y11 contains the following RAM block slices" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a5 " "Info: RAM block slice \"ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a5\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a5 " "Info: RAM block slice \"ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a5\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a4 " "Info: RAM block slice \"ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a4\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a4 " "Info: RAM block slice \"ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a4\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0}  } {  } 2 0 "Physical RAM block %1!s! contains the following RAM block slices" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M4K_X13_Y12 " "Info: Physical RAM block M4K_X13_Y12 contains the following RAM block slices" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a3 " "Info: RAM block slice \"ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a3\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a3 " "Info: RAM block slice \"ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a3\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a2 " "Info: RAM block slice \"ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a2\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a2 " "Info: RAM block slice \"ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a2\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0}  } {  } 2 0 "Physical RAM block %1!s! contains the following RAM block slices" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M4K_X13_Y10 " "Info: Physical RAM block M4K_X13_Y10 contains the following RAM block slices" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a1 " "Info: RAM block slice \"ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a1\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a1 " "Info: RAM block slice \"ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a1\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a0 " "Info: RAM block slice \"ramwave:inst3\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a0\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a0 " "Info: RAM block slice \"ramwave:inst2\|altsyncram:altsyncram_component\|altsyncram_nbl1:auto_generated\|ram_block1a0\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0}  } {  } 2 0 "Physical RAM block %1!s! contains the following RAM block slices" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M4K_X13_Y1 " "Info: Physical RAM block M4K_X13_Y1 contains the following RAM block slices" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a7 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a7\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a7 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a7\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a6 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a6\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a6 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a6\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0}  } {  } 2 0 "Physical RAM block %1!s! contains the following RAM block slices" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M4K_X13_Y4 " "Info: Physical RAM block M4K_X13_Y4 contains the following RAM block slices" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a5 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a5\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a5 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a5\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a4 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a4\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a4 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a4\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0}  } {  } 2 0 "Physical RAM block %1!s! contains the following RAM block slices" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M4K_X13_Y3 " "Info: Physical RAM block M4K_X13_Y3 contains the following RAM block slices" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a3 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a3\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a3 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a3\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a2 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a2\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a2 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a2\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0}  } {  } 2 0 "Physical RAM block %1!s! contains the following RAM block slices" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M4K_X13_Y2 " "Info: Physical RAM block M4K_X13_Y2 contains the following RAM block slices" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a1 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a1\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a1 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a1\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a0 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Iram\|altsyncram:mem_rtl_0\|altsyncram_19i1:auto_generated\|ram_block1a0\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a0 " "Info: RAM block slice \"cfft1024X12:inst1\|cfft:aCfft\|blockdram:Qram\|altsyncram:mem_rtl_1\|altsyncram_19i1:auto_generated\|ram_block1a0\"" {  } {  } 2 0 "RAM block slice \"%1!s!\"" 0 0 "" 0}  } {  } 2 0 "Physical RAM block %1!s! contains the following RAM block slices" 0 0 "" 0}  } {  } 2 0 "Following physical RAM blocks contain multiple logical RAM block slices" 0 0 "" 0}  } {  } 2 0 "Fitter merged %1!d! physical RAM blocks that contain multiple logical RAM block slices into a single location" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "MCUBUS:inst\|process0~0 " "Info: Following pins have the same output enable: MCUBUS:inst\|process0~0" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional p0\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin p0\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 360 264 440 376 "p0\[7..0\]" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "p0\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional p0\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin p0\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 360 264 440 376 "p0\[7..0\]" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "p0\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional p0\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin p0\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 360 264 440 376 "p0\[7..0\]" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "p0\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional p0\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin p0\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 360 264 440 376 "p0\[7..0\]" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "p0\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional p0\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin p0\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 360 264 440 376 "p0\[7..0\]" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "p0\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional p0\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin p0\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 360 264 440 376 "p0\[7..0\]" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "p0\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional p0\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin p0\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 360 264 440 376 "p0\[7..0\]" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "p0\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional p0\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin p0\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 360 264 440 376 "p0\[7..0\]" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "p0\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p0[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "I:/fftinterface/ffti.fit.smsg " "Info: Generated suppressed messages file I:/fftinterface/ffti.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "184 " "Info: Allocated 184 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 05 21:53:00 2007 " "Info: Processing ended: Wed Sep 05 21:53:00 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Info: Elapsed time: 00:00:25" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}