prev_cmp_ffti.tan.qmsg

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

{ "Info" "ITDB_FULL_TPD_RESULT" "cs p0\[4\] 12.368 ns Longest " "Info: Longest tpd from source pin \"cs\" to destination pin \"p0\[4\]\" is 12.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cs 1 PIN PIN_94 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_94; Fanout = 16; PIN Node = 'cs'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cs } "NODE_NAME" } } { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 472 -360 -192 488 "cs" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.538 ns) + CELL(0.442 ns) 7.449 ns MCUBUS:inst\|process0~0 2 COMB LC_X22_Y6_N4 8 " "Info: 2: + IC(5.538 ns) + CELL(0.442 ns) = 7.449 ns; Loc. = LC_X22_Y6_N4; Fanout = 8; COMB Node = 'MCUBUS:inst\|process0~0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.980 ns" { cs MCUBUS:inst|process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.840 ns) + CELL(2.079 ns) 12.368 ns p0\[4\] 3 PIN PIN_71 0 " "Info: 3: + IC(2.840 ns) + CELL(2.079 ns) = 12.368 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'p0\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.919 ns" { MCUBUS:inst|process0~0 p0[4] } "NODE_NAME" } } { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 360 264 440 376 "p0\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.990 ns ( 32.26 % ) " "Info: Total cell delay = 3.990 ns ( 32.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.378 ns ( 67.74 % ) " "Info: Total interconnect delay = 8.378 ns ( 67.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.368 ns" { cs MCUBUS:inst|process0~0 p0[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.368 ns" { cs cs~out0 MCUBUS:inst|process0~0 p0[4] } { 0.000ns 0.000ns 5.538ns 2.840ns } { 0.000ns 1.469ns 0.442ns 2.079ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "MCUBUS:inst\|LATCH_ADDRES\[8\] p2\[0\] ale -0.452 ns register " "Info: th for register \"MCUBUS:inst\|LATCH_ADDRES\[8\]\" (data pin = \"p2\[0\]\", clock pin = \"ale\") is -0.452 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ale destination 6.381 ns + Longest register " "Info: + Longest clock path from clock \"ale\" to destination register is 6.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ale 1 CLK PIN_78 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_78; Fanout = 13; CLK Node = 'ale'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ale } "NODE_NAME" } } { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 408 -360 -192 424 "ale" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.201 ns) + CELL(0.711 ns) 6.381 ns MCUBUS:inst\|LATCH_ADDRES\[8\] 2 REG LC_X26_Y6_N2 2 " "Info: 2: + IC(4.201 ns) + CELL(0.711 ns) = 6.381 ns; Loc. = LC_X26_Y6_N2; Fanout = 2; REG Node = 'MCUBUS:inst\|LATCH_ADDRES\[8\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.912 ns" { ale MCUBUS:inst|LATCH_ADDRES[8] } "NODE_NAME" } } { "MCUBUS.vhd" "" { Text "I:/fftinterface/MCUBUS.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 34.16 % ) " "Info: Total cell delay = 2.180 ns ( 34.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.201 ns ( 65.84 % ) " "Info: Total interconnect delay = 4.201 ns ( 65.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.381 ns" { ale MCUBUS:inst|LATCH_ADDRES[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.381 ns" { ale ale~out0 MCUBUS:inst|LATCH_ADDRES[8] } { 0.000ns 0.000ns 4.201ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "MCUBUS.vhd" "" { Text "I:/fftinterface/MCUBUS.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.848 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns p2\[0\] 1 PIN PIN_85 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_85; Fanout = 1; PIN Node = 'p2\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { p2[0] } "NODE_NAME" } } { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 552 -360 -192 568 "p2\[4..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.070 ns) + CELL(0.309 ns) 6.848 ns MCUBUS:inst\|LATCH_ADDRES\[8\] 2 REG LC_X26_Y6_N2 2 " "Info: 2: + IC(5.070 ns) + CELL(0.309 ns) = 6.848 ns; Loc. = LC_X26_Y6_N2; Fanout = 2; REG Node = 'MCUBUS:inst\|LATCH_ADDRES\[8\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.379 ns" { p2[0] MCUBUS:inst|LATCH_ADDRES[8] } "NODE_NAME" } } { "MCUBUS.vhd" "" { Text "I:/fftinterface/MCUBUS.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 25.96 % ) " "Info: Total cell delay = 1.778 ns ( 25.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.070 ns ( 74.04 % ) " "Info: Total interconnect delay = 5.070 ns ( 74.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.848 ns" { p2[0] MCUBUS:inst|LATCH_ADDRES[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.848 ns" { p2[0] p2[0]~out0 MCUBUS:inst|LATCH_ADDRES[8] } { 0.000ns 0.000ns 5.070ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.381 ns" { ale MCUBUS:inst|LATCH_ADDRES[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.381 ns" { ale ale~out0 MCUBUS:inst|LATCH_ADDRES[8] } { 0.000ns 0.000ns 4.201ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.848 ns" { p2[0] MCUBUS:inst|LATCH_ADDRES[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.848 ns" { p2[0] p2[0]~out0 MCUBUS:inst|LATCH_ADDRES[8] } { 0.000ns 0.000ns 5.070ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 05 21:53:14 2007 " "Info: Processing ended: Wed Sep 05 21:53:14 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}