gen.vht

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

	Q_expected(5) <= '0';
WAIT;
END PROCESS t_prcs_Q_5;
-- expected Q[4]
t_prcs_Q_4: PROCESS
BEGIN
	Q_expected(4) <= '0';
WAIT;
END PROCESS t_prcs_Q_4;
-- expected Q[3]
t_prcs_Q_3: PROCESS
BEGIN
	Q_expected(3) <= '0';
WAIT;
END PROCESS t_prcs_Q_3;
-- expected Q[2]
t_prcs_Q_2: PROCESS
BEGIN
	Q_expected(2) <= '0';
WAIT;
END PROCESS t_prcs_Q_2;
-- expected Q[1]
t_prcs_Q_1: PROCESS
BEGIN
	Q_expected(1) <= '0';
WAIT;
END PROCESS t_prcs_Q_1;
-- expected Q[0]
t_prcs_Q_0: PROCESS
BEGIN
	Q_expected(0) <= '0';
WAIT;
END PROCESS t_prcs_Q_0;
-- expected QOUT[13]
t_prcs_QOUT_13: PROCESS
BEGIN
	QOUT_expected(13) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_13;
-- expected QOUT[12]
t_prcs_QOUT_12: PROCESS
BEGIN
	QOUT_expected(12) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_12;
-- expected QOUT[11]
t_prcs_QOUT_11: PROCESS
BEGIN
	QOUT_expected(11) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_11;
-- expected QOUT[10]
t_prcs_QOUT_10: PROCESS
BEGIN
	QOUT_expected(10) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_10;
-- expected QOUT[9]
t_prcs_QOUT_9: PROCESS
BEGIN
	QOUT_expected(9) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_9;
-- expected QOUT[8]
t_prcs_QOUT_8: PROCESS
BEGIN
	QOUT_expected(8) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_8;
-- expected QOUT[7]
t_prcs_QOUT_7: PROCESS
BEGIN
	QOUT_expected(7) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_7;
-- expected QOUT[6]
t_prcs_QOUT_6: PROCESS
BEGIN
	QOUT_expected(6) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_6;
-- expected QOUT[5]
t_prcs_QOUT_5: PROCESS
BEGIN
	QOUT_expected(5) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_5;
-- expected QOUT[4]
t_prcs_QOUT_4: PROCESS
BEGIN
	QOUT_expected(4) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_4;
-- expected QOUT[3]
t_prcs_QOUT_3: PROCESS
BEGIN
	QOUT_expected(3) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_3;
-- expected QOUT[2]
t_prcs_QOUT_2: PROCESS
BEGIN
	QOUT_expected(2) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_2;
-- expected QOUT[1]
t_prcs_QOUT_1: PROCESS
BEGIN
	QOUT_expected(1) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_1;
-- expected QOUT[0]
t_prcs_QOUT_0: PROCESS
BEGIN
	QOUT_expected(0) <= '0';
WAIT;
END PROCESS t_prcs_QOUT_0;

-- expected RESET
t_prcs_RESET: PROCESS
BEGIN
	RESET_expected <= '0';
	WAIT FOR 16768 ps;
	RESET_expected <= '1';
	WAIT FOR 30000 ps;
	RESET_expected <= '0';
	WAIT FOR 49150000 ps;
	RESET_expected <= '1';
	WAIT FOR 20000 ps;
	RESET_expected <= '0';
	WAIT FOR 50800000 ps;
	RESET_expected <= '1';
	WAIT FOR 20000 ps;
	RESET_expected <= '0';
WAIT;
END PROCESS t_prcs_RESET;

-- expected START
t_prcs_START: PROCESS
BEGIN
	START_expected <= '0';
	WAIT FOR 56486 ps;
	START_expected <= '1';
	WAIT FOR 20000 ps;
	START_expected <= '0';
WAIT;
END PROCESS t_prcs_START;

-- expected WR
t_prcs_WR: PROCESS
BEGIN
	WR_expected <= '0';
WAIT;
END PROCESS t_prcs_WR;

-- Set trigger on real/expected o/ pattern changes                        

t_prcs_trigger_e : PROCESS(ADDR_expected,ADDROUT_expected,INPUTBUSY_expected,IOUT_expected,Q_expected,QOUT_expected,RESET_expected,START_expected,WR_expected)
BEGIN
	trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;

t_prcs_trigger_r : PROCESS(ADDR,ADDROUT,INPUTBUSY,IOUT,Q,QOUT,RESET,START,WR)
BEGIN
	trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;


t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;

VARIABLE last_ADDROUT_exp : STD_LOGIC_VECTOR(9 DOWNTO 0) := "UUUUUUUUUU";
VARIABLE last_INPUTBUSY_exp : STD_LOGIC := 'U';
VARIABLE last_IOUT_exp : STD_LOGIC_VECTOR(13 DOWNTO 0) := "UUUUUUUUUUUUUU";
VARIABLE last_Q_exp : STD_LOGIC_VECTOR(11 DOWNTO 0) := "UUUUUUUUUUUU";
VARIABLE last_QOUT_exp : STD_LOGIC_VECTOR(13 DOWNTO 0) := "UUUUUUUUUUUUUU";
VARIABLE last_RESET_exp : STD_LOGIC := 'U';
VARIABLE last_START_exp : STD_LOGIC := 'U';
VARIABLE last_WR_exp : STD_LOGIC := 'U';

VARIABLE on_first_change : trackvec := "111111111";
BEGIN

WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
	AND sampler'EVENT;
IF (debug_tbench = '1') THEN
	write(txt,string'("Scanning pattern "));
	write(txt,i);
	writeline(output,txt);
	write(txt,string'("| expected "));write(txt,ADDR_name);write(txt,string'(" = "));write(txt,ADDR_expected_prev);
	write(txt,string'("| expected "));write(txt,ADDROUT_name);write(txt,string'(" = "));write(txt,ADDROUT_expected_prev);
	write(txt,string'("| expected "));write(txt,INPUTBUSY_name);write(txt,string'(" = "));write(txt,INPUTBUSY_expected_prev);
	write(txt,string'("| expected "));write(txt,IOUT_name);write(txt,string'(" = "));write(txt,IOUT_expected_prev);
	write(txt,string'("| expected "));write(txt,Q_name);write(txt,string'(" = "));write(txt,Q_expected_prev);
	write(txt,string'("| expected "));write(txt,QOUT_name);write(txt,string'(" = "));write(txt,QOUT_expected_prev);
	write(txt,string'("| expected "));write(txt,RESET_name);write(txt,string'(" = "));write(txt,RESET_expected_prev);
	write(txt,string'("| expected "));write(txt,START_name);write(txt,string'(" = "));write(txt,START_expected_prev);
	write(txt,string'("| expected "));write(txt,WR_name);write(txt,string'(" = "));write(txt,WR_expected_prev);
	writeline(output,txt);
	write(txt,string'("| real "));write(txt,ADDR_name);write(txt,string'(" = "));write(txt,ADDR_prev);
	write(txt,string'("| real "));write(txt,ADDROUT_name);write(txt,string'(" = "));write(txt,ADDROUT_prev);
	write(txt,string'("| real "));write(txt,INPUTBUSY_name);write(txt,string'(" = "));write(txt,INPUTBUSY_prev);
	write(txt,string'("| real "));write(txt,IOUT_name);write(txt,string'(" = "));write(txt,IOUT_prev);
	write(txt,string'("| real "));write(txt,Q_name);write(txt,string'(" = "));write(txt,Q_prev);
	write(txt,string'("| real "));write(txt,QOUT_name);write(txt,string'(" = "));write(txt,QOUT_prev);
	write(txt,string'("| real "));write(txt,RESET_name);write(txt,string'(" = "));write(txt,RESET_prev);
	write(txt,string'("| real "));write(txt,START_name);write(txt,string'(" = "));write(txt,START_prev);
	write(txt,string'("| real "));write(txt,WR_name);write(txt,string'(" = "));write(txt,WR_prev);
	writeline(output,txt);
	i := i + 1;
END IF;
IF ( ADDROUT_expected_prev /= "XXXXXXXXXX" ) AND (ADDROUT_expected_prev /= "UUUUUUUUUU" ) AND (ADDROUT_prev /= ADDROUT_expected_prev) AND (
	(ADDROUT_expected_prev /= last_ADDROUT_exp) OR
	(on_first_change(2) = '1')
		) THEN
	throw_error("ADDROUT",ADDROUT_expected_prev,ADDROUT_prev);
	num_mismatches(1) <= num_mismatches(1) + 1;
	on_first_change(2) := '0';
	last_ADDROUT_exp := ADDROUT_expected_prev;
END IF;
IF ( INPUTBUSY_expected_prev /= 'X' ) AND (INPUTBUSY_expected_prev /= 'U' ) AND (INPUTBUSY_prev /= INPUTBUSY_expected_prev) AND (
	(INPUTBUSY_expected_prev /= last_INPUTBUSY_exp) OR
	(on_first_change(3) = '1')
		) THEN
	throw_error("INPUTBUSY",INPUTBUSY_expected_prev,INPUTBUSY_prev);
	num_mismatches(2) <= num_mismatches(2) + 1;
	on_first_change(3) := '0';
	last_INPUTBUSY_exp := INPUTBUSY_expected_prev;
END IF;
IF ( IOUT_expected_prev /= "XXXXXXXXXXXXXX" ) AND (IOUT_expected_prev /= "UUUUUUUUUUUUUU" ) AND (IOUT_prev /= IOUT_expected_prev) AND (
	(IOUT_expected_prev /= last_IOUT_exp) OR
	(on_first_change(4) = '1')
		) THEN
	throw_error("IOUT",IOUT_expected_prev,IOUT_prev);
	num_mismatches(3) <= num_mismatches(3) + 1;
	on_first_change(4) := '0';
	last_IOUT_exp := IOUT_expected_prev;
END IF;
IF ( Q_expected_prev /= "XXXXXXXXXXXX" ) AND (Q_expected_prev /= "UUUUUUUUUUUU" ) AND (Q_prev /= Q_expected_prev) AND (
	(Q_expected_prev /= last_Q_exp) OR
	(on_first_change(5) = '1')
		) THEN
	throw_error("Q",Q_expected_prev,Q_prev);
	num_mismatches(4) <= num_mismatches(4) + 1;
	on_first_change(5) := '0';
	last_Q_exp := Q_expected_prev;
END IF;
IF ( QOUT_expected_prev /= "XXXXXXXXXXXXXX" ) AND (QOUT_expected_prev /= "UUUUUUUUUUUUUU" ) AND (QOUT_prev /= QOUT_expected_prev) AND (
	(QOUT_expected_prev /= last_QOUT_exp) OR
	(on_first_change(6) = '1')
		) THEN
	throw_error("QOUT",QOUT_expected_prev,QOUT_prev);
	num_mismatches(5) <= num_mismatches(5) + 1;
	on_first_change(6) := '0';
	last_QOUT_exp := QOUT_expected_prev;
END IF;
IF ( RESET_expected_prev /= 'X' ) AND (RESET_expected_prev /= 'U' ) AND (RESET_prev /= RESET_expected_prev) AND (
	(RESET_expected_prev /= last_RESET_exp) OR
	(on_first_change(7) = '1')
		) THEN
	throw_error("RESET",RESET_expected_prev,RESET_prev);
	num_mismatches(6) <= num_mismatches(6) + 1;
	on_first_change(7) := '0';
	last_RESET_exp := RESET_expected_prev;
END IF;
IF ( START_expected_prev /= 'X' ) AND (START_expected_prev /= 'U' ) AND (START_prev /= START_expected_prev) AND (
	(START_expected_prev /= last_START_exp) OR
	(on_first_change(8) = '1')
		) THEN
	throw_error("START",START_expected_prev,START_prev);
	num_mismatches(7) <= num_mismatches(7) + 1;
	on_first_change(8) := '0';
	last_START_exp := START_expected_prev;
END IF;
IF ( WR_expected_prev /= 'X' ) AND (WR_expected_prev /= 'U' ) AND (WR_prev /= WR_expected_prev) AND (
	(WR_expected_prev /= last_WR_exp) OR
	(on_first_change(9) = '1')
		) THEN
	throw_error("WR",WR_expected_prev,WR_prev);
	num_mismatches(8) <= num_mismatches(8) + 1;
	on_first_change(9) := '0';
	last_WR_exp := WR_expected_prev;
END IF;
    trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;


t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
	trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;

t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 130000000 ps;
total_mismatches := num_mismatches(0) + num_mismatches(1) + num_mismatches(2) + num_mismatches(3) + num_mismatches(4) + num_mismatches(5) + num_mismatches(6) + num_mismatches(7) + num_mismatches(8);
IF (total_mismatches = 0) THEN                                              
        write(txt,string'("Simulation passed !"));                        
        writeline(output,txt);                                              
ELSE                                                                        
        write(txt,total_mismatches);                                        
        write(txt,string'(" mismatched vectors : Simulation failed !"));  
        writeline(output,txt);                                              
END IF;                                                                     
WAIT;
END PROCESS t_prcs_endsim;

END ovec_arch;

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

LIBRARY STD;                                                            
USE STD.textio.ALL;                                                     

USE WORK.TEST1_vhd_tb_types.ALL;                                         

ENTITY TEST1_vhd_vec_tst IS
END TEST1_vhd_vec_tst;
ARCHITECTURE TEST1_arch OF TEST1_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL ADDR : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL ADDROUT : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL CLK : STD_LOGIC;
SIGNAL INPUTBUSY : STD_LOGIC;
SIGNAL IOUT : STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL Q : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL QOUT : STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL RESET : STD_LOGIC;
SIGNAL ST : STD_LOGIC;
SIGNAL START : STD_LOGIC;
SIGNAL WR : STD_LOGIC;
SIGNAL sampler : sample_type;

COMPONENT TEST1
	PORT (
	ADDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
	ADDROUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
	CLK : IN STD_LOGIC;
	INPUTBUSY : OUT STD_LOGIC;
	IOUT : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
	Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
	QOUT : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
	RESET : OUT STD_LOGIC;
	ST : IN STD_LOGIC;
	START : OUT STD_LOGIC;
	WR : OUT STD_LOGIC
	);
END COMPONENT;
COMPONENT TEST1_vhd_check_tst
PORT (
	ADDR : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
	ADDROUT : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
	INPUTBUSY : IN STD_LOGIC;
	IOUT : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
	Q : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
	QOUT : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
	RESET : IN STD_LOGIC;
	START : IN STD_LOGIC;
	WR : IN STD_LOGIC;
	sampler : IN sample_type
);
END COMPONENT;
COMPONENT TEST1_vhd_sample_tst
PORT (
	CLK : IN STD_LOGIC;
	ST : IN STD_LOGIC;
	sampler : OUT sample_type
	);
END COMPONENT;
BEGIN
	i1 : TEST1
	PORT MAP (
-- list connections between master ports and signals
	ADDR => ADDR,
	ADDROUT => ADDROUT,
	CLK => CLK,
	INPUTBUSY => INPUTBUSY,
	IOUT => IOUT,
	Q => Q,
	QOUT => QOUT,
	RESET => RESET,
	ST => ST,
	START => START,
	WR => WR
	);

-- CLK
t_prcs_CLK: PROCESS
BEGIN
LOOP
	CLK <= '0';
	WAIT FOR 5000 ps;
	CLK <= '1';
	WAIT FOR 5000 ps;
	IF (NOW >= 130000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_CLK;

-- ST
t_prcs_ST: PROCESS
BEGIN
	ST <= '1';
	WAIT FOR 20000 ps;
	ST <= '0';
WAIT;
END PROCESS t_prcs_ST;
tb_sample : TEST1_vhd_sample_tst
PORT MAP (
	CLK => CLK,
	ST => ST,
	sampler => sampler
	);

tb_out : TEST1_vhd_check_tst
PORT MAP (
	ADDR => ADDR,
	ADDROUT => ADDROUT,
	INPUTBUSY => INPUTBUSY,
	IOUT => IOUT,
	Q => Q,
	QOUT => QOUT,
	RESET => RESET,
	START => START,
	WR => WR,
	sampler => sampler
	);
END TEST1_arch;