📄 gen.vht
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-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors
-- are exported from a vector file in the Quartus Waveform Editor and apply to
-- the top level entity of the current Quartus project .The user can use this
-- testbench to simulate his design using a third-party simulation tool .
-- *****************************************************************************
-- Generated on "09/04/2007 00:05:04"
-- Vhdl Self-Checking Test Bench (with test vectors) for design : TEST1
--
-- Simulation tool : 3rd Party
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
PACKAGE TEST1_vhd_tb_types IS
-- input port types
-- output port names
CONSTANT ADDR_name : STRING (1 TO 4) := "ADDR";
CONSTANT ADDROUT_name : STRING (1 TO 7) := "ADDROUT";
CONSTANT INPUTBUSY_name : STRING (1 TO 9) := "INPUTBUSY";
CONSTANT IOUT_name : STRING (1 TO 4) := "IOUT";
CONSTANT Q_name : STRING (1 TO 1) := "Q";
CONSTANT QOUT_name : STRING (1 TO 4) := "QOUT";
CONSTANT RESET_name : STRING (1 TO 5) := "RESET";
CONSTANT START_name : STRING (1 TO 5) := "START";
CONSTANT WR_name : STRING (1 TO 2) := "WR";
-- n(outputs)
CONSTANT o_num : INTEGER := 9;
-- mismatches vector type
TYPE mmvec IS ARRAY (0 to (o_num - 1)) OF INTEGER;
-- exp o/ first change track vector type
TYPE trackvec IS ARRAY (1 to o_num) OF BIT;
-- sampler type
SUBTYPE sample_type IS STD_LOGIC;
-- utility functions
FUNCTION std_logic_to_char (a: STD_LOGIC) RETURN CHARACTER;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR) RETURN STRING;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR);
END TEST1_vhd_tb_types;
PACKAGE BODY TEST1_vhd_tb_types IS
FUNCTION std_logic_to_char (a: STD_LOGIC)
RETURN CHARACTER IS
BEGIN
CASE a IS
WHEN 'U' =>
RETURN 'U';
WHEN 'X' =>
RETURN 'X';
WHEN '0' =>
RETURN '0';
WHEN '1' =>
RETURN '1';
WHEN 'Z' =>
RETURN 'Z';
WHEN 'W' =>
RETURN 'W';
WHEN 'L' =>
RETURN 'L';
WHEN 'H' =>
RETURN 'H';
WHEN '-' =>
RETURN 'D';
END CASE;
END;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR)
RETURN STRING IS
VARIABLE result : STRING(1 TO a'LENGTH);
VARIABLE j : NATURAL := 1;
BEGIN
FOR i IN a'RANGE LOOP
result(j) := std_logic_to_char(a(i));
j := j + 1;
END LOOP;
RETURN result;
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:=RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_to_char(VALUE),JUSTIFIED,field);
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_vector_to_string(VALUE),JUSTIFIED,field);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
write(txt,string'(", Expected value = "));
write(txt,expected_value);
write(txt,string'(", Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
write(txt,string'(", Expected value = "));
write(txt,expected_value);
write(txt,string'(", Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
END TEST1_vhd_tb_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE WORK.TEST1_vhd_tb_types.ALL;
ENTITY TEST1_vhd_sample_tst IS
PORT (
CLK : IN STD_LOGIC;
ST : IN STD_LOGIC;
sampler : OUT sample_type
);
END TEST1_vhd_sample_tst;
ARCHITECTURE sample_arch OF TEST1_vhd_sample_tst IS
SIGNAL tbo_int_sample_clk : sample_type := '1';
BEGIN
t_prcs_sample : PROCESS ( CLK , ST )
BEGIN
IF (NOW > 0 ps) AND (NOW < 130000000 ps) THEN
tbo_int_sample_clk <= NOT tbo_int_sample_clk ;
END IF;
END PROCESS t_prcs_sample;
sampler <= tbo_int_sample_clk;
END sample_arch;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.TEST1_vhd_tb_types.ALL;
ENTITY TEST1_vhd_check_tst IS
GENERIC (
debug_tbench : BIT := '0'
);
PORT (
ADDR : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
ADDROUT : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
INPUTBUSY : IN STD_LOGIC;
IOUT : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
Q : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
QOUT : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
RESET : IN STD_LOGIC;
START : IN STD_LOGIC;
WR : IN STD_LOGIC;
sampler : IN sample_type
);
END TEST1_vhd_check_tst;
ARCHITECTURE ovec_arch OF TEST1_vhd_check_tst IS
SIGNAL ADDR_expected,ADDR_expected_prev,ADDR_prev : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL ADDROUT_expected,ADDROUT_expected_prev,ADDROUT_prev : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL INPUTBUSY_expected,INPUTBUSY_expected_prev,INPUTBUSY_prev : STD_LOGIC;
SIGNAL IOUT_expected,IOUT_expected_prev,IOUT_prev : STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL Q_expected,Q_expected_prev,Q_prev : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL QOUT_expected,QOUT_expected_prev,QOUT_prev : STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL RESET_expected,RESET_expected_prev,RESET_prev : STD_LOGIC;
SIGNAL START_expected,START_expected_prev,START_prev : STD_LOGIC;
SIGNAL WR_expected,WR_expected_prev,WR_prev : STD_LOGIC;
SIGNAL trigger : BIT := '0';
SIGNAL trigger_e : BIT := '0';
SIGNAL trigger_r : BIT := '0';
SIGNAL trigger_i : BIT := '0';
SIGNAL num_mismatches : mmvec := (OTHERS => 0);
BEGIN
-- Update history buffers expected /o
t_prcs_update_o_expected_hist : PROCESS (trigger)
BEGIN
ADDR_expected_prev <= ADDR_expected;
ADDROUT_expected_prev <= ADDROUT_expected;
INPUTBUSY_expected_prev <= INPUTBUSY_expected;
IOUT_expected_prev <= IOUT_expected;
Q_expected_prev <= Q_expected;
QOUT_expected_prev <= QOUT_expected;
RESET_expected_prev <= RESET_expected;
START_expected_prev <= START_expected;
WR_expected_prev <= WR_expected;
END PROCESS t_prcs_update_o_expected_hist;
-- Update history buffers real /o
t_prcs_update_o_real_hist : PROCESS (trigger)
BEGIN
ADDR_prev <= ADDR;
ADDROUT_prev <= ADDROUT;
INPUTBUSY_prev <= INPUTBUSY;
IOUT_prev <= IOUT;
Q_prev <= Q;
QOUT_prev <= QOUT;
RESET_prev <= RESET;
START_prev <= START;
WR_prev <= WR;
END PROCESS t_prcs_update_o_real_hist;
-- expected ADDROUT[9]
t_prcs_ADDROUT_9: PROCESS
BEGIN
ADDROUT_expected(9) <= '0';
WAIT;
END PROCESS t_prcs_ADDROUT_9;
-- expected ADDROUT[8]
t_prcs_ADDROUT_8: PROCESS
BEGIN
ADDROUT_expected(8) <= '0';
WAIT;
END PROCESS t_prcs_ADDROUT_8;
-- expected ADDROUT[7]
t_prcs_ADDROUT_7: PROCESS
BEGIN
ADDROUT_expected(7) <= '0';
WAIT;
END PROCESS t_prcs_ADDROUT_7;
-- expected ADDROUT[6]
t_prcs_ADDROUT_6: PROCESS
BEGIN
ADDROUT_expected(6) <= '0';
WAIT;
END PROCESS t_prcs_ADDROUT_6;
-- expected ADDROUT[5]
t_prcs_ADDROUT_5: PROCESS
BEGIN
ADDROUT_expected(5) <= '0';
WAIT;
END PROCESS t_prcs_ADDROUT_5;
-- expected ADDROUT[4]
t_prcs_ADDROUT_4: PROCESS
BEGIN
ADDROUT_expected(4) <= '0';
WAIT;
END PROCESS t_prcs_ADDROUT_4;
-- expected ADDROUT[3]
t_prcs_ADDROUT_3: PROCESS
BEGIN
ADDROUT_expected(3) <= '0';
WAIT;
END PROCESS t_prcs_ADDROUT_3;
-- expected ADDROUT[2]
t_prcs_ADDROUT_2: PROCESS
BEGIN
ADDROUT_expected(2) <= '0';
WAIT;
END PROCESS t_prcs_ADDROUT_2;
-- expected ADDROUT[1]
t_prcs_ADDROUT_1: PROCESS
BEGIN
ADDROUT_expected(1) <= '0';
WAIT;
END PROCESS t_prcs_ADDROUT_1;
-- expected ADDROUT[0]
t_prcs_ADDROUT_0: PROCESS
BEGIN
ADDROUT_expected(0) <= '0';
WAIT;
END PROCESS t_prcs_ADDROUT_0;
-- expected INPUTBUSY
t_prcs_INPUTBUSY: PROCESS
BEGIN
INPUTBUSY_expected <= '0';
WAIT FOR 61821 ps;
INPUTBUSY_expected <= '1';
WAIT FOR 49140627 ps;
INPUTBUSY_expected <= '0';
WAIT;
END PROCESS t_prcs_INPUTBUSY;
-- expected IOUT[13]
t_prcs_IOUT_13: PROCESS
BEGIN
IOUT_expected(13) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_13;
-- expected IOUT[12]
t_prcs_IOUT_12: PROCESS
BEGIN
IOUT_expected(12) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_12;
-- expected IOUT[11]
t_prcs_IOUT_11: PROCESS
BEGIN
IOUT_expected(11) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_11;
-- expected IOUT[10]
t_prcs_IOUT_10: PROCESS
BEGIN
IOUT_expected(10) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_10;
-- expected IOUT[9]
t_prcs_IOUT_9: PROCESS
BEGIN
IOUT_expected(9) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_9;
-- expected IOUT[8]
t_prcs_IOUT_8: PROCESS
BEGIN
IOUT_expected(8) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_8;
-- expected IOUT[7]
t_prcs_IOUT_7: PROCESS
BEGIN
IOUT_expected(7) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_7;
-- expected IOUT[6]
t_prcs_IOUT_6: PROCESS
BEGIN
IOUT_expected(6) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_6;
-- expected IOUT[5]
t_prcs_IOUT_5: PROCESS
BEGIN
IOUT_expected(5) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_5;
-- expected IOUT[4]
t_prcs_IOUT_4: PROCESS
BEGIN
IOUT_expected(4) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_4;
-- expected IOUT[3]
t_prcs_IOUT_3: PROCESS
BEGIN
IOUT_expected(3) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_3;
-- expected IOUT[2]
t_prcs_IOUT_2: PROCESS
BEGIN
IOUT_expected(2) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_2;
-- expected IOUT[1]
t_prcs_IOUT_1: PROCESS
BEGIN
IOUT_expected(1) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_1;
-- expected IOUT[0]
t_prcs_IOUT_0: PROCESS
BEGIN
IOUT_expected(0) <= '0';
WAIT;
END PROCESS t_prcs_IOUT_0;
-- expected Q[11]
t_prcs_Q_11: PROCESS
BEGIN
Q_expected(11) <= '0';
WAIT;
END PROCESS t_prcs_Q_11;
-- expected Q[10]
t_prcs_Q_10: PROCESS
BEGIN
Q_expected(10) <= '0';
WAIT;
END PROCESS t_prcs_Q_10;
-- expected Q[9]
t_prcs_Q_9: PROCESS
BEGIN
Q_expected(9) <= '0';
WAIT;
END PROCESS t_prcs_Q_9;
-- expected Q[8]
t_prcs_Q_8: PROCESS
BEGIN
Q_expected(8) <= '0';
WAIT;
END PROCESS t_prcs_Q_8;
-- expected Q[7]
t_prcs_Q_7: PROCESS
BEGIN
Q_expected(7) <= '0';
WAIT;
END PROCESS t_prcs_Q_7;
-- expected Q[6]
t_prcs_Q_6: PROCESS
BEGIN
Q_expected(6) <= '0';
WAIT;
END PROCESS t_prcs_Q_6;
-- expected Q[5]
t_prcs_Q_5: PROCESS
BEGIN
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