ffti.sim.rpt

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

; Simulation results format                                                                  ; CVWF          ;               ;
; Vector input source                                                                        ; Waveform1.vwf ;               ;
; Add pins automatically to simulation output waveforms                                      ; On            ; On            ;
; Check outputs                                                                              ; Off           ; Off           ;
; Report simulation coverage                                                                 ; On            ; On            ;
; Display complete 1/0 value coverage report                                                 ; On            ; On            ;
; Display missing 1-value coverage report                                                    ; On            ; On            ;
; Display missing 0-value coverage report                                                    ; On            ; On            ;
; Detect setup and hold time violations                                                      ; Off           ; Off           ;
; Detect glitches                                                                            ; Off           ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off           ; Off           ;
; Generate Signal Activity File                                                              ; Off           ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off           ; Off           ;
; Group bus channels in simulation results                                                   ; Off           ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On            ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE    ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off           ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; On            ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto          ; Auto          ;
+--------------------------------------------------------------------------------------------+---------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------------------------------------+
; |Block1|ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ALTSYNCRAM ;
+--------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------------------------------------------------------+
; |Block1|cfft1024X12:inst1|cfft:aCfft|blockdram:Qram|altsyncram:mem_rtl_1|altsyncram_19i1:auto_generated|ALTSYNCRAM ;
+--------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------------------------------------------------------+
; |Block1|cfft1024X12:inst1|cfft:aCfft|blockdram:Iram|altsyncram:mem_rtl_0|altsyncram_19i1:auto_generated|ALTSYNCRAM ;
+--------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      96.05 % ;
; Total nodes checked                                 ; 1484         ;
; Total output ports checked                          ; 2935         ;
; Total output ports with complete 1/0-value coverage ; 2819         ;
; Total output ports with no 1/0-value coverage       ; 110          ;
; Total output ports with no 1-value coverage         ; 111          ;
; Total output ports with no 0-value coverage         ; 115          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.