ffti.tan.rpt

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

; Type                         ; Slack ; Required Time ; Actual Time                      ; From                                                                                                           ; To                                       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------+------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 8.248 ns                         ; rd                                                                                                             ; MCUBUS:inst|DATAOUT[3]                   ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 8.562 ns                         ; MCUBUS:inst|OE                                                                                                 ; p0[3]                                    ; clk        ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 12.368 ns                        ; cs                                                                                                             ; p0[3]                                    ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.452 ns                        ; p2[0]                                                                                                          ; MCUBUS:inst|LATCH_ADDRES[8]              ; --         ; ale      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 98.50 MHz ( period = 10.152 ns ) ; ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a1~porta_address_reg10 ; ff:inst8|lpm_ff:lpm_ff_component|dffs[0] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                                ;                                          ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------+------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ale             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;