gen.vhd

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY GEN IS
	PORT(   CLK:IN STD_LOGIC;
			ST:IN STD_LOGIC;
			INPUTBUSY:IN STD_LOGIC;
			
			FINISH:OUT STD_LOGIC;
			RST:OUT STD_LOGIC;
			START:OUT STD_LOGIC;
			ADDRRD:OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
			
		);
END GEN;
ARCHITECTURE ART OF GEN IS
TYPE STATE is (ST_ST0,ST_ST1,ST_RESET,ST_RESETWAIT,ST_START,ST_SENDWAIT,ST_SEND);
SIGNAL CURSTATE, NEXTSTATE: STATE;
SIGNAL CONT:INTEGER RANGE 0 TO 2047;
BEGIN
	PROCESS(CLK,ST)
	BEGIN
		IF CLK'EVENT AND CLK='1' THEN
			CURSTATE<=NEXTSTATE;
		END IF;
	END PROCESS;
	PROCESS(CLK)
	BEGIN
		IF CLK'EVENT AND CLK='1' THEN
			IF CURSTATE=ST_SEND THEN
				CONT<=CONT+1;
			ELSE
				CONT<=0;
			END IF;
		END IF;
	END PROCESS;
	PROCESS(CLK)
	BEGIN
		IF CLK'EVENT AND CLK='0' THEN
			CASE CURSTATE IS
				WHEN ST_ST0=>
					RST<='0';
					START<='0';
					FINISH<='1';
					IF ST='1' THEN
						NEXTSTATE<=ST_ST1;
					END IF;
				WHEN ST_ST1=>
					RST<='0';
					START<='0';
					FINISH<='1';
					IF ST='0' THEN
						NEXTSTATE<=ST_RESET;
					END IF;
				WHEN ST_RESET=>
					RST<='1';
					START<='0';
					FINISH<='0';
					IF ST='0' THEN
						NEXTSTATE<=ST_RESETWAIT;
					END IF;
					
				WHEN ST_RESETWAIT=>
					RST<='0';
					START<='0';
					FINISH<='0';
					NEXTSTATE<=ST_START;
				WHEN ST_START=>
					RST<='0';
					START<='1';
					FINISH<='0';
					NEXTSTATE<=ST_SENDWAIT;
				WHEN ST_SENDWAIT=>
					RST<='0';
					START<='0';
					FINISH<='0';
					IF INPUTBUSY='1' THEN
						NEXTSTATE<=ST_SEND;
					END IF;
				WHEN ST_SEND=>
					RST<='0';
					START<='0';
					FINISH<='0';
					ADDRRD<=CONV_STD_LOGIC_VECTOR(CONT,11);
					IF INPUTBUSY='0' THEN
						NEXTSTATE<=ST_ST0;
					END IF;
			END CASE;

		END IF;
	END PROCESS;

END ART;