ffti.fit.rpt

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; Slow Slew Rate                                                     ; Off                            ; Off                            ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                              ;
+------------------------------------------+-----------------+------------------+---------------------+-----------+--------------------------------------------------------------------------------------+------------------+
; Node                                     ; Action          ; Operation        ; Reason              ; Node Port ; Destination Node                                                                     ; Destination Port ;
+------------------------------------------+-----------------+------------------+---------------------+-----------+--------------------------------------------------------------------------------------+------------------+
; ff:inst8|lpm_ff:lpm_ff_component|dffs[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|q_a[0] ; PORTADATAOUT     ;
; ff:inst8|lpm_ff:lpm_ff_component|dffs[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|q_a[1] ; PORTADATAOUT     ;
; ff:inst8|lpm_ff:lpm_ff_component|dffs[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|q_a[2] ; PORTADATAOUT     ;
; ff:inst8|lpm_ff:lpm_ff_component|dffs[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|q_a[3] ; PORTADATAOUT     ;
; ff:inst8|lpm_ff:lpm_ff_component|dffs[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|q_a[4] ; PORTADATAOUT     ;
; ff:inst8|lpm_ff:lpm_ff_component|dffs[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|q_a[5] ; PORTADATAOUT     ;
; ff:inst8|lpm_ff:lpm_ff_component|dffs[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|q_a[6] ; PORTADATAOUT     ;
; ff:inst8|lpm_ff:lpm_ff_component|dffs[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|q_a[7] ; PORTADATAOUT     ;
+------------------------------------------+-----------------+------------------+---------------------+-----------+--------------------------------------------------------------------------------------+------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in I:/fftinterface/ffti.pin.


+-------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                   ;
+---------------------------------------------+---------------------------------------------------+
; Resource                                    ; Usage                                             ;
+---------------------------------------------+---------------------------------------------------+
; Total logic elements                        ; 1,485 / 2,910 ( 51 % )                            ;
;     -- Combinational with no register       ; 516                                               ;
;     -- Register only                        ; 144                                               ;
;     -- Combinational with a register        ; 825                                               ;
;                                             ;                                                   ;
; Logic element usage by number of LUT inputs ;                                                   ;
;     -- 4 input functions                    ; 99                                                ;
;     -- 3 input functions                    ; 719                                               ;
;     -- 2 input functions                    ; 466                                               ;
;     -- 1 input functions                    ; 120                                               ;
;     -- 0 input functions                    ; 81                                                ;
;                                             ;                                                   ;
; Logic elements by mode                      ;                                                   ;
;     -- normal mode                          ; 640                                               ;
;     -- arithmetic mode                      ; 845                                               ;
;     -- qfbk mode                            ; 23                                                ;
;     -- register cascade mode                ; 0                                                 ;
;     -- synchronous clear/load mode          ; 359                                               ;
;     -- asynchronous clear/load mode         ; 175                                               ;
;                                             ;                                                   ;
; Total registers                             ; 969 / 3,210 ( 30 % )                              ;
; Total LABs                                  ; 193 / 291 ( 66 % )                                ;
; Logic elements in carry chains              ; 913                                               ;
; User inserted logic elements                ; 0                                                 ;
; Virtual pins                                ; 0                                                 ;
; I/O pins                                    ; 18 / 104 ( 17 % )                                 ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )                                    ;
; Global signals                              ; 3                                                 ;
; M4Ks                                        ; 12 / 13 ( 92 % )                                  ;
; Total memory bits                           ; 49,152 / 59,904 ( 82 % )                          ;
; Total RAM block bits                        ; 55,296 / 59,904 ( 92 % )                          ;
; PLLs                                        ; 0 / 1 ( 0 % )                                     ;
; Global clocks                               ; 3 / 8 ( 38 % )                                    ;
; Average interconnect usage                  ; 20%                                               ;