mux.vhd

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUX IS
	PORT(CLK:IN STD_LOGIC;
		 ADDRIN:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
		 OUTDATAEN:IN STD_LOGIC;
		 ADDROUT:OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
		 WRHIGH:OUT STD_LOGIC;
		 WRLOW:OUT STD_LOGIC
		);
END MUX;
ARCHITECTURE ART OF MUX IS
BEGIN
	PROCESS(CLK,ADDRIN)
	BEGIN
		IF CLK'EVENT AND CLK='1' THEN
			IF OUTDATAEN='1' THEN
				ADDROUT<=ADDRIN(8 DOWNTO 0);
				IF ADDRIN(9)='0' THEN
					WRLOW<='1';
					WRHIGH<='0';
				ELSE
					WRLOW<='0';
					WRHIGH<='1';
				END IF;
			ELSE
				WRLOW<='0';
				WRHIGH<='0';
			END IF;
		END IF;
	END PROCESS;
END ART;