ffti.map.rpt

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP1C3T144C8        ;                    ;
; Top-level entity name                                                          ; ffti               ; ffti               ;
; Family name                                                                    ; Cyclone            ; Stratix II         ;
; Use smart compilation                                                          ; On                 ; Off                ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone                                              ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM Block Balancing                                                       ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                       ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                       ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; ff.vhd                           ; yes             ; User VHDL File                     ; I:/fftinterface/ff.vhd                                             ;
; ramdata.vhd                      ; yes             ; User VHDL File                     ; I:/fftinterface/ramdata.vhd                                        ;
; ramwave.vhd                      ; yes             ; User VHDL File                     ; I:/fftinterface/ramwave.vhd                                        ;
; TRANS.vhd                        ; yes             ; User VHDL File                     ; I:/fftinterface/TRANS.vhd                                          ;
; address.vhd                      ; yes             ; User VHDL File                     ; I:/fftinterface/address.vhd                                        ;
; blockdram.vhd                    ; yes             ; User VHDL File                     ; I:/fftinterface/blockdram.vhd                                      ;
; cfft.vhd                         ; yes             ; User VHDL File                     ; I:/fftinterface/cfft.vhd                                           ;
; cfft1024X12.vhd                  ; yes             ; User VHDL File                     ; I:/fftinterface/cfft1024X12.vhd                                    ;
; cfft4.vhd                        ; yes             ; User VHDL File                     ; I:/fftinterface/cfft4.vhd                                          ;
; div4limit.vhd                    ; yes             ; User VHDL File                     ; I:/fftinterface/div4limit.vhd                                      ;
; mulfactor.vhd                    ; yes             ; User VHDL File                     ; I:/fftinterface/mulfactor.vhd                                      ;
; p2r_cordic.vhd                   ; yes             ; User VHDL File                     ; I:/fftinterface/p2r_cordic.vhd                                     ;
; p2r_CordicPipe.vhd               ; yes             ; User VHDL File                     ; I:/fftinterface/p2r_CordicPipe.vhd                                 ;
; rofactor.vhd                     ; yes             ; User VHDL File                     ; I:/fftinterface/rofactor.vhd                                       ;
; sc_corproc.vhd                   ; yes             ; User VHDL File                     ; I:/fftinterface/sc_corproc.vhd                                     ;
; MCUBUS.vhd                       ; yes             ; User VHDL File                     ; I:/fftinterface/MCUBUS.vhd                                         ;
; ffti.bdf                         ; yes             ; User Block Diagram/Schematic File  ; I:/fftinterface/ffti.bdf                                           ;
; GEN.vhd                          ; yes             ; User VHDL File                     ; I:/fftinterface/GEN.vhd                                            ;
; lpm_ff.tdf                       ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf            ;
; lpm_constant.inc                 ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/lpm_constant.inc      ;
; aglobal71.inc                    ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/aglobal71.inc         ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/lpm_decode.inc        ;
; a_rdenreg.inc                    ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/altram.inc            ;