mcubus.vhd

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
ENTITY MCUBUS IS
	PORT(P0		: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		 ALE	: IN STD_LOGIC;
		 RD		: IN STD_LOGIC;
		 WR		: IN STD_LOGIC;
		 CLK	: IN STD_LOGIC;
		 CS		: IN STD_LOGIC;
		 
		 FINISH 	:IN STD_LOGIC;
		
		 ADDRDATA   :OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
		 WROUT		:OUT STD_LOGIC;
		 DATAWR		:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		 DATARD		:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		
		 ADDR		:OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
		 DATARDLOW		:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		 DATARDHIGH     :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		 ST			:OUT STD_LOGIC;
		 P2		: IN STD_LOGIC_VECTOR(4 DOWNTO 0));
END MCUBUS;
ARCHITECTURE ART OF MCUBUS IS
  SIGNAL LATCH_ADDRES:	STD_LOGIC_VECTOR(12 DOWNTO 0);
  SIGNAL DATAOUT,DATAIN:STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL OE:			STD_LOGIC;
BEGIN


PROCESS (OE,CS,P0,DATAOUT)           
    BEGIN 
		IF( OE = '0'  OR  CS='1' ) THEN
			P0 <= "ZZZZZZZZ";
		ELSE
			P0 <= DATAOUT; 
		END IF;
END PROCESS;
PROCESS(ALE)                    
BEGIN
  IF ALE'EVENT AND ALE='0' THEN
      LATCH_ADDRES<=P2 & P0;
  END IF;
END PROCESS;
PROCESS(CLK)
  BEGIN
	IF (CLK'EVENT AND CLK='1') THEN
		IF CS='0' THEN
			ADDR<=LATCH_ADDRES(9 DOWNTO 0);
			ADDRDATA<=LATCH_ADDRES(10 DOWNTO 0);
		END IF;
	END IF;
END PROCESS;

PROCESS(CLK,RD)
  BEGIN
	IF (CLK'EVENT AND CLK='1') THEN
		IF RD='0' AND CS='0' THEN 
			IF LATCH_ADDRES(12 DOWNTO 11)="00" THEN
					DATAOUT<=DATARD;
			ELSIF LATCH_ADDRES(12 DOWNTO 10)="100" THEN
					DATAOUT<=DATARDLOW;
			ELSIF LATCH_ADDRES(12 DOWNTO 10)="101" THEN
					DATAOUT<=DATARDHIGH;
			ELSIF LATCH_ADDRES="1111111111111" THEN
				DATAOUT<="0000000" & FINISH;
			END IF;
			OE<='1';
		ELSE
			OE<='0';
		END IF;
	END IF;
END PROCESS;
PROCESS(CLK,WR)
  BEGIN
	IF (CLK'EVENT AND CLK='1') THEN
		IF  WR='0' AND CS='0' THEN
			IF LATCH_ADDRES(12 DOWNTO 11)="00" THEN
				DATAWR(7 DOWNTO 0)<=P0;
				WROUT<='1';
	   		ELSIF LATCH_ADDRES="1111111111111" THEN
				ST<=P0(0);
			END IF;
		ELSE
			WROUT<='0';
		END IF;
	END IF;
END PROCESS;
END ART;