dpram_rpg1.tdf

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

--altdpram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" INDATA_ACLR="OFF" INDATA_REG="INCLOCK" NUMWORDS=1024 OUTDATA_ACLR="OFF" OUTDATA_REG="OUTCLOCK" RDADDRESS_ACLR="OFF" RDADDRESS_REG="INCLOCK" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" USE_EAB="ON" WIDTH=12 WIDTHAD=10 WRADDRESS_ACLR="OFF" WRADDRESS_REG="INCLOCK" WRCONTROL_ACLR="OFF" WRCONTROL_REG="INCLOCK" data inclock outclock q rdaddress wraddress wren CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 7.1 cbx_altdpram 2007:03:30:09:43:02:SJ cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END


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--  without limitation, that your use is for the sole purpose of 
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FUNCTION altsyncram_bko1 (address_a[9..0], address_b[9..0], clock0, clock1, data_a[11..0], wren_a)
RETURNS ( q_b[11..0]);

--synthesis_resources = M4K 3 
SUBDESIGN dpram_rpg1
( 
	data[11..0]	:	input;
	inclock	:	input;
	outclock	:	input;
	q[11..0]	:	output;
	rdaddress[9..0]	:	input;
	wraddress[9..0]	:	input;
	wren	:	input;
) 
VARIABLE 
	altsyncram1 : altsyncram_bko1;

BEGIN 
	altsyncram1.address_a[] = wraddress[];
	altsyncram1.address_b[] = rdaddress[];
	altsyncram1.clock0 = inclock;
	altsyncram1.clock1 = outclock;
	altsyncram1.data_a[] = data[];
	altsyncram1.wren_a = wren;
	q[] = altsyncram1.q_b[];
	ASSERT (0) 
	REPORT "ALTDPRAM doesn't support Stratix. Trying for best case memory conversions. The power up states will be different for stratix as well as read during write modes"
	SEVERITY WARNING;
END;
--VALID FILE