ffti.hif

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

USR
pipeid
8
PARAMETER_SIGNED_DEC
USR
 constraint(xi)
19 downto 0
PARAMETER_STRING
USR
 constraint(yi)
19 downto 0
PARAMETER_STRING
USR
 constraint(zi)
19 downto 0
PARAMETER_STRING
USR
 constraint(xo)
19 downto 0
PARAMETER_STRING
USR
 constraint(yo)
19 downto 0
PARAMETER_STRING
USR
 constraint(zo)
19 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
p2r_CordicPipe
# storage
db|ffti.(21).cnf
db|ffti.(21).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
p2r_CordicPipe.vhd
6619d5fa79d97e895521a97112a6a7de
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
width
20
PARAMETER_SIGNED_DEC
USR
pipeid
9
PARAMETER_SIGNED_DEC
USR
 constraint(xi)
19 downto 0
PARAMETER_STRING
USR
 constraint(yi)
19 downto 0
PARAMETER_STRING
USR
 constraint(zi)
19 downto 0
PARAMETER_STRING
USR
 constraint(xo)
19 downto 0
PARAMETER_STRING
USR
 constraint(yo)
19 downto 0
PARAMETER_STRING
USR
 constraint(zo)
19 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
p2r_CordicPipe
# storage
db|ffti.(22).cnf
db|ffti.(22).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
p2r_CordicPipe.vhd
6619d5fa79d97e895521a97112a6a7de
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
width
20
PARAMETER_SIGNED_DEC
USR
pipeid
10
PARAMETER_SIGNED_DEC
USR
 constraint(xi)
19 downto 0
PARAMETER_STRING
USR
 constraint(yi)
19 downto 0
PARAMETER_STRING
USR
 constraint(zi)
19 downto 0
PARAMETER_STRING
USR
 constraint(xo)
19 downto 0
PARAMETER_STRING
USR
 constraint(yo)
19 downto 0
PARAMETER_STRING
USR
 constraint(zo)
19 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
p2r_CordicPipe
# storage
db|ffti.(23).cnf
db|ffti.(23).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
p2r_CordicPipe.vhd
6619d5fa79d97e895521a97112a6a7de
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
width
20
PARAMETER_SIGNED_DEC
USR
pipeid
11
PARAMETER_SIGNED_DEC
USR
 constraint(xi)
19 downto 0
PARAMETER_STRING
USR
 constraint(yi)
19 downto 0
PARAMETER_STRING
USR
 constraint(zi)
19 downto 0
PARAMETER_STRING
USR
 constraint(xo)
19 downto 0
PARAMETER_STRING
USR
 constraint(yo)
19 downto 0
PARAMETER_STRING
USR
 constraint(zo)
19 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
rofactor
# storage
db|ffti.(24).cnf
db|ffti.(24).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rofactor.vhd
31c25e4ce61cc11eb2f7827ff34eca8
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
point
1024
PARAMETER_SIGNED_DEC
USR
stage
5
PARAMETER_SIGNED_DEC
USR
 constraint(angle)
9 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
cfft1024X12:inst1|cfft:aCfft|rofactor:arofactor
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
altsyncram
# storage
db|ffti.(26).cnf
db|ffti.(26).cnf
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|altsyncram.tdf
b69478c2691550fb7f5ef3923da937a
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
12
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
10
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
1024
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
12
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
10
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
1024
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
ramwave.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_knn1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|71|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
c:|altera|71|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|71|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|71|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|71|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
c:|altera|71|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|71|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
c:|altera|71|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altsyncram
# storage
db|ffti.(29).cnf
db|ffti.(29).cnf
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|altsyncram.tdf
b69478c2691550fb7f5ef3923da937a
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
14
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
512
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
14
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
512
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
test.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_a1n1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|71|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
c:|altera|71|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|71|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|71|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|71|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
c:|altera|71|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|71|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
c:|altera|71|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altsyncram_a1n1
# storage