music_parameter.v

来自「基于FPGA的VHDL编程实现各种音频信号」· Verilog 代码 · 共 18 行

// music_parameter.v
/****************************************************************************************
Here's essentially the same code. A new parameter named "clkdivider" was added, and the 
counter was changed into a "count-down" counter - just a matter of preference.
****************************************************************************************/

module music_parameter(clk, speaker);
input clk;
output speaker;
parameter clkdivider = 25000000/440/2;

reg [14:0] counter;
always @(posedge clk) if(counter==0) counter <= clkdivider-1; else counter <= counter-1;

reg speaker;
always @(posedge clk) if(counter==0) speaker <= ~speaker;

endmodule