music_police_siren.v

来自「基于FPGA的VHDL编程实现各种音频信号」· Verilog 代码 · 共 27 行

// music_police_siren.v       //警笛鸣声   
 
module music_police_siren(clk, speaker);
input clk;
output speaker;
//
reg [22:0] tone;
always @(posedge clk) tone <= tone+1;

/*
This way, "clkdivider" have a value ranging from 15'b010000000000000 
to 15'b011111111000000, or in hex 15'h2000 to 15'h3FC0, or in decimal 
8192 to 16320. With a 25MHz input clock, that produces "speaker" from 765Hz to 1525Hz.
 That gives us a high pitch siren.

*/
wire [6:0] ramp = (tone[22] ? tone[21:15] : ~tone[21:15]);    //25000000/16320=1532HZ /2=765
                                                              //25000000/8192=1525*2(1525HZ)
wire [14:0] clkdivider = {2'b01, ramp, 6'b000000};

reg [14:0] counter;
always @(posedge clk) if(counter==0) counter <= clkdivider; else counter <= counter-1;

reg speaker;
always @(posedge clk) if(counter==0) speaker <= ~speaker;

endmodule