key_measure.v

来自「基于FPGA的VHDL编程实现各种音频信号」· Verilog 代码 · 共 58 行

// key_measure.v
//功能:消除抖动
//     每触发按一次键,键值加1
module key_measure(
                    clk,
                    rst_n,     //高电平复位
                    key_in,
                    key_out
                   );
input  clk;
input  rst_n;
input  key_in;
output [3:0]   key_out;


//--中间变量声明-----
reg  [16:0]  cnt;
reg          dout1,dout2,dout3;
wire          key_done;

always @(posedge clk)
begin
if (!rst_n)
    cnt<=0;
else
    cnt<=cnt+'d1;
end

always @(posedge cnt[16])
begin
      dout1<=key_in;
      dout2<=dout1;
      dout3<=dout2;
end
assign key_done=dout1&dout2&dout3;

//键值输出
reg    [3:0]   key_temp;
always @(posedge key_done or negedge rst_n)
begin
       if(!rst_n)
         key_temp<='d0;
       else
         if(key_temp>=4'd8)
            key_temp<=4'd1;
         else
            key_temp<=key_temp+'d1;

end

assign key_out=key_temp;






endmodule