music_simple_beep.v

来自「基于FPGA的VHDL编程实现各种音频信号」· Verilog 代码 · 共 30 行

// music_simple_beep.v
/***************************************************************************************
name    :      music_simple_beep
describe:
FPGAs can easily implement binary counters. Let's start with a 16-bits counter.
Starting from the 25MHz clock, we can simply "divide the clock" using the counter. 
A 16 bits counter counts from 0 to 65535 (65536 different values). The highest bit
of the counter toggles at a frequency of 25000000/65536=381Hz.

The LSB (counter[0]) would toggle with a frequency of 12.5MHz. "counter[1]" with 6.125MHz.
And so on. We use the MSB (bit 15) of the counter to drive the output. Here it goes! a nice
381Hz square signal comes out of the "speaker" output.

data    :     2008.2.22
ceator  :      Yehua.Li
****************************************************************************************/

module music_simple_beep(clk, speaker);
input clk;
output speaker;

// Binary counter, 16-bits wide
reg [15:0] counter;
always @(posedge clk) counter <= counter+1;

// Use the highest bit of the counter (MSB) to drive the speaker
assign speaker = counter[15];

endmodule