music_440hz.v

来自「基于FPGA的VHDL编程实现各种音频信号」· Verilog 代码 · 共 23 行

// music_440HZ.v
/*********************************************************************************
There is a problem though. The frequency is 440Hz, as expected, but the output 
duty cycle is not 50% anymore. The low level goes from counter=0 to counter=32767 
(when bit 15 of counter is low) and then high level from 32768 to 56817. That gives
 us "speaker" being high only 42% of the time.
The easiest way to get a 50% duty cycle is to add a stage that divides the output by 2.
 So first we divide by 28409 (instead of 56818) and then by 2.
***********************************************************************************/
module music_440HZ(
                   clk, 
                   speaker
                   );
input clk;
output speaker;

reg [14:0] counter;
always @(posedge clk) if(counter==28408) counter <= 0; else counter <= counter+1;

reg speaker;
always @(posedge clk) if(counter==28408) speaker <= ~speaker;

endmodule