main_drc.rpt

基于FPGA的VHDL编程实现各种音频信号

=====================================================================
Parameters used to run compile:
===============================

Family      : Fusion
Device      : AFS600
Package     : 256 FBGA
Source      : F:\Actel_prj\myprj\simple_beep\synthesis\main.edn
Format      : EDIF
Topcell     : main
Speed grade : -2
Temp        : 0:25:70
Voltage     : 1.58:1.50:1.42


=====================================================================
Compile starts ...

Warning: CMP201: Net: PLL_25M_U0/Core_GLB is floating
Warning: CMP201: Net: PLL_25M_U0/Core_GLC is floating
Warning: CMP201: Net: PLL_25M_U0/Core_LOCK is floating
Warning: CMP201: Net: PLL_25M_U0/Core_YB is floating
Warning: CMP201: Net: PLL_25M_U0/Core_YC is floating

Netlist Optimization Report
===========================

Optimized macros:
  - Dangling net drivers:   0
  - Buffers:                1
  - Inverters:              0
  - Tieoff:                 0
  - Logic combining:        63

    Total macros optimized  64

There were 0 error(s) and 5 warning(s) in this design.
=====================================================================
Compile report:
===============

    CORE                     Used:    987  Total:  13824   (7.14%)
    IO (W/ clocks)           Used:     12  Total:    119   (10.08%)
    Differential IO          Used:      0  Total:     58   (0.00%)
    GLOBAL (Chip+Quadrant)   Used:      1  Total:     18   (5.56%)
    PLL                      Used:      1  Total:      2   (50.00%)
    RAM/FIFO                 Used:      0  Total:     24   (0.00%)
    Low Static ICC           Used:      0  Total:      1   (0.00%)
    FlashROM                 Used:      0  Total:      1   (0.00%)
    User JTAG                Used:      0  Total:      1   (0.00%)
    RC oscillator            Used:      0  Total:      1   (0.00%)
    XTL oscillator           Used:      0  Total:      1   (0.00%)
    NVM                      Used:      0  Total:      2   (0.00%)
    AB                       Used:      0  Total:      1   (0.00%)
    AnalogIO                 Used:      0  Total:     46   (0.00%)
    VRPSM                    Used:      0  Total:      1   (0.00%)
    No-Glitch MUX            Used:      0  Total:      2   (0.00%)

Global Information:

    Type            | Used   | Total
    ----------------|--------|-------------
    Chip global     | 1      | 6  (16.67%)
    Quadrant global | 0      | 12 (0.00%)

Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 732          | 732
    SEQ     | 255          | 255

I/O Function:

    Type                          | w/o register  | w/ register  | w/ DDR register
    ------------------------------|---------------|--------------|----------------
    Input I/O                     | 3             | 0            | 0
    Output I/O                    | 9             | 0            | 0
    Bidirectional I/O             | 0             | 0            | 0
    Differential Input I/O Pairs  | 0             | 0            | 0
    Differential Output I/O Pairs | 0             | 0            | 0

I/O Technology:

                                    |   Voltages    |             I/Os
    --------------------------------|-------|-------|-------|--------|--------------
    I/O Standard(s)                 | Vcci  | Vref  | Input | Output | Bidirectional
    --------------------------------|-------|-------|-------|--------|--------------
    LVTTL                           | 3.30v | N/A   | 3     | 9      | 0

Net information report:
=======================

The following nets have been assigned to a chip global resource:
    Fanout  Type          Name
    --------------------------
    248     CLK_NET       Net   : clk_25m
                          Driver: PLL_25M_U0/Core
                          Source: ESSENTIAL

High fanout nets in the post compile netlist:
    Fanout  Type          Name
    --------------------------
    12      INT_NET       Net   : U5/counter_note11
                          Driver: U5/counter_note11
    12      INT_NET       Net   : U5/note[2]
                          Driver: U5/divby12/m9
    12      INT_NET       Net   : U5/counter_note11_0
                          Driver: U5/counter_note11_0
    12      INT_NET       Net   : U2/counter15_12
                          Driver: U2/counter15_12
    12      INT_NET       Net   : U2/counter15_11
                          Driver: U2/counter15_11
    11      INT_NET       Net   : rst_K2_c
                          Driver: rst_K2_pad
    11      INT_NET       Net   : rst_K2_c_0
                          Driver: rst_K2_pad_0
    11      INT_NET       Net   : U5/note[0]
                          Driver: U5/tone[22]
    11      INT_NET       Net   : U1/counter15_13
                          Driver: U1/counter15_13
    11      INT_NET       Net   : U1/counter15_12
                          Driver: U1/counter15_12

Nets that are candidates for clock assignment and the resulting fanout:
    Fanout  Type          Name
    --------------------------
    21      INT_NET       Net   : rst_K2_c
                          Driver: rst_K2_pad
    12      INT_NET       Net   : U5/counter_note11
                          Driver: U5/counter_note11
    12      INT_NET       Net   : U5/note[2]
                          Driver: U5/divby12/m9
    12      INT_NET       Net   : U5/counter_note11_0
                          Driver: U5/counter_note11_0
    12      INT_NET       Net   : U2/counter15_12
                          Driver: U2/counter15_12
    12      INT_NET       Net   : U2/counter15_11
                          Driver: U2/counter15_11
    11      INT_NET       Net   : U5/note[0]
                          Driver: U5/tone[22]
    11      INT_NET       Net   : U1/counter15_13
                          Driver: U1/counter15_13
    11      INT_NET       Net   : U1/counter15_12
                          Driver: U1/counter15_12
    10      INT_NET       Net   : U7/tone[22]
                          Driver: U7/tone[22]


SDC Import: Starting final constraints validation...


The Compile command succeeded ( 00:00:06 )