music_simple_beep_drc.rpt

基于FPGA的VHDL编程实现各种音频信号

=====================================================================
Parameters used to run compile:
===============================

Family      : Fusion
Device      : AFS600
Package     : 256 FBGA
Source      : F:\Actel_prj\myprj\simple_beep\synthesis\music_simple_beep.edn
Format      : EDIF
Topcell     : music_simple_beep
Speed grade : -2
Temp        : 0:25:70
Voltage     : 1.58:1.50:1.42


=====================================================================
Compile starts ...


Netlist Optimization Report
===========================

Optimized macros:
  - Dangling net drivers:   0
  - Buffers:                0
  - Inverters:              0
  - Tieoff:                 0
  - Logic combining:        0

    Total macros optimized  0

There were 0 error(s) and 0 warning(s) in this design.
=====================================================================
Compile report:
===============

    CORE                     Used:     55  Total:  13824   (0.40%)
    IO (W/ clocks)           Used:      2  Total:    119   (1.68%)
    Differential IO          Used:      0  Total:     58   (0.00%)
    GLOBAL (Chip+Quadrant)   Used:      0  Total:     18   (0.00%)
    PLL                      Used:      0  Total:      2   (0.00%)
    RAM/FIFO                 Used:      0  Total:     24   (0.00%)
    Low Static ICC           Used:      0  Total:      1   (0.00%)
    FlashROM                 Used:      0  Total:      1   (0.00%)
    User JTAG                Used:      0  Total:      1   (0.00%)
    RC oscillator            Used:      0  Total:      1   (0.00%)
    XTL oscillator           Used:      0  Total:      1   (0.00%)
    NVM                      Used:      0  Total:      2   (0.00%)
    AB                       Used:      0  Total:      1   (0.00%)
    AnalogIO                 Used:      0  Total:     46   (0.00%)
    VRPSM                    Used:      0  Total:      1   (0.00%)
    No-Glitch MUX            Used:      0  Total:      2   (0.00%)

Global Information:

    Type            | Used   | Total
    ----------------|--------|-------------
    Chip global     | 0      | 6  (0.00%)
    Quadrant global | 0      | 12 (0.00%)

Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 39           | 39
    SEQ     | 16           | 16

I/O Function:

    Type                          | w/o register  | w/ register  | w/ DDR register
    ------------------------------|---------------|--------------|----------------
    Input I/O                     | 1             | 0            | 0
    Output I/O                    | 1             | 0            | 0
    Bidirectional I/O             | 0             | 0            | 0
    Differential Input I/O Pairs  | 0             | 0            | 0
    Differential Output I/O Pairs | 0             | 0            | 0

I/O Technology:

                                    |   Voltages    |             I/Os
    --------------------------------|-------|-------|-------|--------|--------------
    I/O Standard(s)                 | Vcci  | Vref  | Input | Output | Bidirectional
    --------------------------------|-------|-------|-------|--------|--------------
    LVTTL                           | 3.30v | N/A   | 1     | 1      | 0

Net information report:
=======================

High fanout nets in the post compile netlist:
    Fanout  Type          Name
    --------------------------
    12      INT_NET       Net   : counter_c1
                          Driver: counter_c1
    11      INT_NET       Net   : counter_c3_s
                          Driver: counter_c3_s
    9       CLK_NET       Net   : clk_c
                          Driver: clk_pad
    8       CLK_NET       Net   : clk_c_0
                          Driver: clk_pad_0
    4       INT_NET       Net   : counter_c5_s
                          Driver: counter_c5_s
    4       INT_NET       Net   : counter_c11_s_0_0
                          Driver: counter_c11_s_0
    3       INT_NET       Net   : counter[0]
                          Driver: counter[0]
    3       INT_NET       Net   : counter[2]
                          Driver: counter[2]
    3       INT_NET       Net   : counter[4]
                          Driver: counter[4]
    3       INT_NET       Net   : counter[6]
                          Driver: counter[6]

Nets that are candidates for clock assignment and the resulting fanout:
    Fanout  Type          Name
    --------------------------
    16      CLK_NET       Net   : clk_c
                          Driver: clk_pad
    12      INT_NET       Net   : counter_c1
                          Driver: counter_c1
    11      INT_NET       Net   : counter_c3_s
                          Driver: counter_c3_s
    4       INT_NET       Net   : counter_c5_s
                          Driver: counter_c5_s
    4       INT_NET       Net   : counter_c11_s_0_0
                          Driver: counter_c11_s_0
    3       INT_NET       Net   : counter[0]
                          Driver: counter[0]
    3       INT_NET       Net   : counter[2]
                          Driver: counter[2]
    3       INT_NET       Net   : counter[4]
                          Driver: counter[4]
    3       INT_NET       Net   : counter[6]
                          Driver: counter[6]
    3       INT_NET       Net   : counter[7]
                          Driver: counter[7]


SDC Import: Starting final constraints validation...


The Compile command succeeded ( 00:00:03 )