music_simple_beep.areasrr

基于FPGA的VHDL编程实现各种音频信号

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Report for cell music_simple_beep.verilog
                                          Cell usage:
                               cell       count     area    count*area
                                AX1         3       1.0        3.0
                               AX1B         2       1.0        2.0
                               AX1C         7       1.0        7.0
                               BUFF         1       1.0        1.0
                               DFN1        16       1.0       16.0
                                GND         1       0.0        0.0
                              INBUF         1       0.0        0.0
                                INV         1       1.0        1.0
                               NOR2         2       1.0        2.0
                              NOR2A         4       1.0        4.0
                              NOR2B         5       1.0        5.0
                              NOR3A         4       1.0        4.0
                              NOR3C         3       1.0        3.0
                                OR2         1       1.0        1.0
                               OR2B         3       1.0        3.0
                             OUTBUF         1       0.0        0.0
                                VCC         1       0.0        0.0
                              XNOR2         1       1.0        1.0
                               XOR2         2       1.0        2.0
                            
                         TOTAL             59                 55.0