music_simple_beep.srr

基于FPGA的VHDL编程实现各种音频信号

#Build: Synplify 8.8A1, Build 015R, Apr 16 2007
#install: C:\Actel\Libero8.0\Synplify\Synplify_88A1
#OS: Windows XP 5.1
#Hostname: MICROSOF-30888C

#Implementation: synthesis

#Fri Feb 22 12:56:00 2008

$ Start of Compile
#Fri Feb 22 12:56:00 2008

Synplicity Verilog Compiler, version 3.7.5, Build 159R, built Apr 13 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@I::"C:\Actel\Libero8.0\Synplify\Synplify_88A1\lib\proasic\fusion.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\music_simple_beep.v"
Verilog syntax check successful!
Selecting top level module music_simple_beep
@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\music_simple_beep.v":18:7:18:23|Synthesizing module music_simple_beep

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Feb 22 12:56:01 2008

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Synplicity Proasic Technology Mapper, Version 8.8.0, Build 015R, Built Apr 15 2007 16:31:14
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8A1
@N: MF249 |Running in 32-bit mode.
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK0": remove clock marking
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK1": remove clock marking
@W: BN154 |View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 40MB peak: 41MB)
@N:"f:\actel_prj\myprj\simple_beep\hdl\music_simple_beep.v":24:0:24:5|Found counter in view:work.music_simple_beep(verilog) inst counter[15:0]

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 40MB peak: 41MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 40MB peak: 41MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 40MB peak: 41MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 41MB peak: 41MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 41MB peak: 41MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)
Buffering clk_c, fanout 16 segments 2

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)

Added 1 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)
Writing Analyst data base F:\Actel_prj\myprj\simple_beep\synthesis\music_simple_beep.srm
@N: BN225 |Writing default property annotation file F:\Actel_prj\myprj\simple_beep\synthesis\music_simple_beep.map.
Writing EDIF Netlist and constraint files
Found clock music_simple_beep|clk with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Feb 22 12:56:06 2008
#


Top view:               music_simple_beep
Library name:           fusion
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        fusion
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 4.616

                          Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock            Frequency     Frequency     Period        Period        Slack     Type         Group              
----------------------------------------------------------------------------------------------------------------------------
music_simple_beep|clk     100.0 MHz     185.7 MHz     10.000        5.384         4.616     inferred     Inferred_clkgroup_0
============================================================================================================================





Clock Relationships
*******************

Clocks                                        |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------
Starting               Ending                 |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------
music_simple_beep|clk  music_simple_beep|clk  |  10.000      4.616  |  No paths    -      |  No paths    -      |  No paths    -    
====================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: music_simple_beep|clk
====================================



Starting Points with Worst Slack
********************************

                Starting                                                   Arrival          
Instance        Reference                 Type     Pin     Net             Time        Slack
                Clock                                                                       
--------------------------------------------------------------------------------------------
counter[4]      music_simple_beep|clk     DFN1     Q       counter[4]      0.476       4.616
counter[0]      music_simple_beep|clk     DFN1     Q       counter[0]      0.476       4.649
counter[5]      music_simple_beep|clk     DFN1     Q       counter[5]      0.476       4.852
counter[2]      music_simple_beep|clk     DFN1     Q       counter[2]      0.476       4.885
counter[1]      music_simple_beep|clk     DFN1     Q       counter[1]      0.476       4.885
counter[3]      music_simple_beep|clk     DFN1     Q       counter[3]      0.476       5.120
counter[7]      music_simple_beep|clk     DFN1     Q       counter[7]      0.476       5.167
counter[6]      music_simple_beep|clk     DFN1     Q       counter[6]      0.476       5.247
counter[8]      music_simple_beep|clk     DFN1     Q       counter[8]      0.476       5.402
counter[12]     music_simple_beep|clk     DFN1     Q       counter[12]     0.476       5.419
============================================================================================


Ending Points with Worst Slack
******************************

                Starting                                                   Required          
Instance        Reference                 Type     Pin     Net             Time         Slack
                Clock                                                                        
---------------------------------------------------------------------------------------------
counter[12]     music_simple_beep|clk     DFN1     D       counter_n12     9.690        4.616
counter[13]     music_simple_beep|clk     DFN1     D       counter_n13     9.690        4.616
counter[14]     music_simple_beep|clk     DFN1     D       counter_n14     9.690        4.616
counter[15]     music_simple_beep|clk     DFN1     D       counter_n15     9.690        4.616
counter[11]     music_simple_beep|clk     DFN1     D       counter_n11     9.690        4.649
counter[8]      music_simple_beep|clk     DFN1     D       counter_n8      9.690        4.728
counter[9]      music_simple_beep|clk     DFN1     D       counter_n9      9.690        4.728
counter[7]      music_simple_beep|clk     DFN1     D       counter_n7      9.590        4.744
counter[10]     music_simple_beep|clk     DFN1     D       counter_n10     9.590        4.947
counter[5]      music_simple_beep|clk     DFN1     D       counter_n5      9.690        5.108
=============================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        10.000
    - Setup time:                            0.310
    = Required time:                         9.690

    - Propagation time:                      5.074
    = Slack (critical) :                     4.616

    Number of logic level(s):                4
    Starting point:                          counter[4] / Q
    Ending point:                            counter[12] / D
    The start point is clocked by            music_simple_beep|clk [rising] on pin CLK
    The end   point is clocked by            music_simple_beep|clk [rising] on pin CLK

Instance / Net                    Pin      Pin               Arrival     No. of    
Name                    Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
counter[4]              DFN1      Q        Out     0.476     0.476       -         
counter[4]              Net       -        -       0.562     -           3         
counter_c5_s            NOR2B     B        In      -         1.038       -         
counter_c5_s            NOR2B     Y        Out     0.460     1.498       -         
counter_c5_s            Net       -        -       0.721     -           4         
counter_c11_s_0_1       NOR3C     C        In      -         2.219       -         
counter_c11_s_0_1       NOR3C     Y        Out     0.484     2.704       -         
counter_c11_s_0_1_0     Net       -        -       0.239     -           1         
counter_c11_s_0         NOR3C     C        In      -         2.943       -         
counter_c11_s_0         NOR3C     Y        Out     0.484     3.427       -         
counter_c11_s_0_0       Net       -        -       0.721     -           4         
counter_n12             AX1C      A        In      -         4.149       -         
counter_n12             AX1C      Y        Out     0.686     4.835       -         
counter_n12             Net       -        -       0.239     -           1         
counter[12]             DFN1      D        In      -         5.074       -         
===================================================================================
Total path delay (propagation time + setup) of 5.384 is 2.901(53.9%) logic and 2.483(46.1%) route.



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Report for cell music_simple_beep.verilog
  Core Cell usage:
              cell count     area count*area
               AX1     3      1.0        3.0
              AX1B     2      1.0        2.0
              AX1C     7      1.0        7.0
              BUFF     1      1.0        1.0
               GND     1      0.0        0.0
               INV     1      1.0        1.0
              NOR2     2      1.0        2.0
             NOR2A     4      1.0        4.0
             NOR2B     5      1.0        5.0
             NOR3A     4      1.0        4.0
             NOR3C     3      1.0        3.0
               OR2     1      1.0        1.0
              OR2B     3      1.0        3.0
               VCC     1      0.0        0.0
             XNOR2     1      1.0        1.0
              XOR2     2      1.0        2.0


              DFN1    16      1.0       16.0
                   -----          ----------
             TOTAL    57                55.0


  IO Cell usage:
              cell count
             INBUF     1
            OUTBUF     1
                   -----
             TOTAL     2


Core Cells         : 55 of 613824 (0%)
IO Cells           : 2 of 172 (1%)

RAM/ROM Usage Summary
Block Rams : 0 of 24 (0%)

Mapper successful!
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Fri Feb 22 12:56:06 2008

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