music_simple_beep.srs

基于FPGA的VHDL编程实现各种音频信号

@E
@ 
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.7.5, Build 159R from Synplicity, Inc.
# Copyright 1994-2007 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Feb 22 12:56:01 2008
#
#
#OPTIONS:"|-fixsmult|-autosm|-I|F:\\Actel_prj\\myprj\\simple_beep\\synthesis\\|-I|C:\\Actel\\Libero8.0\\Synplify\\Synplify_88A1\\lib|-v95|-devicelib|C:\\Actel\\Libero8.0\\Synplify\\Synplify_88A1\\lib\\proasic\\fusion.v|-autosm|-fid2|-sharing|on|-encrypt|-ui|-ram|-ll|2000"
#CUR:"C:\\Actel\\Libero8.0\\Synplify\\Synplify_88A1\\bin\\c_ver.exe":1176452670
#CUR:"C:\\Actel\\Libero8.0\\Synplify\\Synplify_88A1\\lib\\proasic\\fusion.v":1149579214
#CUR:"F:\\Actel_prj\\myprj\\simple_beep\\hdl\\music_simple_beep.v":1203656134
f "C:\Actel\Libero8.0\Synplify\Synplify_88A1\lib\proasic\fusion.v"; # file 0
af .is_verilog 1;
f "F:\Actel_prj\myprj\simple_beep\hdl\music_simple_beep.v"; # file 1
af .is_verilog 1;
@E
@ 
ftell;
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;

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