main_syn.prd

基于FPGA的VHDL编程实现各种音频信号

#-- Synplicity, Inc.
#-- Version Synplify 8.8A1
#-- Project file F:\Actel_prj\myprj\simple_beep\synthesis\main_syn.prd
#-- Written on Fri Feb 22 15:41:47 2008

#
### Watch Implementation type ###
#
watch_impl -all
#
### Watch Implementation properties ###
#
watch_prop -clear