music_simple_beep_syn.prj

基于FPGA的VHDL编程实现各种音频信号

#add_file options
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/music_simple_beep.v"

#device options
set_option -technology Fusion
set_option -part AFS600

#compilation/mapping options
set_option -symbolic_fsm_compiler true

#compilation/mapping options
set_option -frequency 100.000

#simulation options
impl -active "synthesis"
project -result_file "F:/Actel_prj/myprj/simple_beep/synthesis/music_simple_beep.edn"