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Detailed Report for Clock: main|PLL_25M_U0.clk_25m_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------
U5.tone[26] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 Q tone[26] 0.476 1.029
U5.tone[27] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 Q tone[27] 0.476 1.080
U5.tone[25] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 Q tone[25] 0.476 1.118
U5.counter_note[0] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 Q counter_note[0] 0.476 2.408
U7.tone[6] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 Q tone[6] 0.476 2.456
U5.counter_note[1] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 Q counter_note[1] 0.476 2.665
U5.tone[24] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 Q tone[24] 0.476 2.726
U5.tone[7] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 Q tone[7] 0.476 2.745
U5.counter_note[2] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 Q counter_note[2] 0.476 2.829
U5.tone[9] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 Q tone[9] 0.476 2.951
========================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------
U5.counter_note[3] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 D counter_note_n3 9.590 1.029
U5.counter_note[4] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 D counter_note_n4 9.590 1.404
U5.counter_note[2] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 D counter_note_n2 9.590 1.445
U5.counter_note[5] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 D counter_note_n5 9.590 1.628
U5.counter_note[6] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 D counter_note_n6 9.590 1.681
U5.counter_note[0] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 D counter_note_n0 9.590 2.062
U5.counter_note[7] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 D counter_note_n7 9.590 2.387
U7.tone[27] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 D tone_n27 9.690 2.456
U5.counter_note[1] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 D counter_note_n1 9.590 2.579
U5.tone[27] main|PLL_25M_U0.clk_25m_inferred_clock DFN1 D tone_n27 9.690 2.745
=========================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 8.561
= Slack (critical) : 1.029
Number of logic level(s): 7
Starting point: U5.tone[26] / Q
Ending point: U5.counter_note[3] / D
The start point is clocked by main|PLL_25M_U0.clk_25m_inferred_clock [rising] on pin CLK
The end point is clocked by main|PLL_25M_U0.clk_25m_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
U5.tone[26] DFN1 Q Out 0.476 0.476 -
tone[26] Net - - 1.261 - 8
U5.divby12.m5 AO14 C In - 1.737 -
U5.divby12.m5 AO14 Y Out 0.830 2.567 -
N_19 Net - - 0.402 - 2
U5.divby12.m9 MX2B B In - 2.969 -
U5.divby12.m9 MX2B Y Out 0.444 3.413 -
note[2] Net - - 1.663 - 12
U5.clkdivider_0_a2[7] NOR2 B In - 5.076 -
U5.clkdivider_0_a2[7] NOR2 Y Out 0.474 5.550 -
N_89 Net - - 0.402 - 2
U5.clkdivider_i_a2_0[3] NOR2B A In - 5.952 -
U5.clkdivider_i_a2_0[3] NOR2B Y Out 0.384 6.336 -
clkdivider_i_a2_0[3] Net - - 0.239 - 1
U5.clkdivider_i[3] NOR3 B In - 6.575 -
U5.clkdivider_i[3] NOR3 Y Out 0.526 7.101 -
clkdivider_i[3] Net - - 0.239 - 1
U5.counter_note_10 MX2C A In - 7.340 -
U5.counter_note_10 MX2C Y Out 0.429 7.770 -
counter_note_10 Net - - 0.239 - 1
U5.counter_note_n3 AX1A C In - 8.009 -
U5.counter_note_n3 AX1A Y Out 0.313 8.322 -
counter_note_n3 Net - - 0.239 - 1
U5.counter_note[3] DFN1 D In - 8.561 -
=======================================================================================
Total path delay (propagation time + setup) of 8.971 is 4.286(47.8%) logic and 4.685(52.2%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell main.verilog
Core Cell usage:
cell count area count*area
AND2 10 1.0 10.0
AND3 51 1.0 51.0
AO1 1 1.0 1.0
AO14 1 1.0 1.0
AO16 1 1.0 1.0
AO17 1 1.0 1.0
AO1B 1 1.0 1.0
AOI1 6 1.0 6.0
AOI1B 25 1.0 25.0
AX1 5 1.0 5.0
AX1A 6 1.0 6.0
AX1B 3 1.0 3.0
AX1C 60 1.0 60.0
AXO5 1 1.0 1.0
BUFF 1 1.0 1.0
GND 12 0.0 0.0
INV 8 1.0 8.0
MX2 24 1.0 24.0
MX2A 3 1.0 3.0
MX2B 2 1.0 2.0
MX2C 16 1.0 16.0
NOR2 21 1.0 21.0
NOR2A 32 1.0 32.0
NOR2B 109 1.0 109.0
NOR3 15 1.0 15.0
NOR3A 7 1.0 7.0
NOR3B 11 1.0 11.0
NOR3C 43 1.0 43.0
OA1 4 1.0 4.0
OA1A 1 1.0 1.0
OAI1 1 1.0 1.0
OR2 44 1.0 44.0
OR2A 1 1.0 1.0
OR2B 14 1.0 14.0
OR3 68 1.0 68.0
OR3A 2 1.0 2.0
OR3B 3 1.0 3.0
OR3C 8 1.0 8.0
PLL 1 0.0 0.0
PLLINT 1 0.0 0.0
VCC 12 0.0 0.0
XNOR2 77 1.0 77.0
XOR2 108 1.0 108.0
DFN1 243 1.0 243.0
DFN1C1 4 1.0 4.0
DFN1E0 8 1.0 8.0
----- ----------
TOTAL 1076 1050.0
IO Cell usage:
cell count
INBUF 3
OUTBUF 9
-----
TOTAL 12
Core Cells : 1050 of 613824 (0%)
IO Cells : 12 of 172 (7%)
RAM/ROM Usage Summary
Block Rams : 0 of 24 (0%)
Mapper successful!
Process took 0h:00m:10s realtime, 0h:00m:06s cputime
# Fri Feb 22 19:01:51 2008
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