traplog.tlg

基于FPGA的VHDL编程实现各种音频信号

@N: CD630 :".\gentmp0a00300":4:7:4:9|Synthesizing work.top.gen 
@N: CD630 :"syng0a00300":1366:7:1366:9|Synthesizing work.dec.fdec 
@W: CD638 :"syng0a00300":1387:9:1387:13|Signal carry is undriven 
@W: CD638 :"syng0a00300":1388:9:1388:12|Signal asup is undriven 
@W: CD638 :"syng0a00300":1388:15:1388:18|Signal ssup is undriven 
@N: CD630 :"syng0a00300":357:7:357:22|Synthesizing work.dwact_bl_fincdec.impl1 
@W: CD280 :"syng0a00300":369:12:369:14|Unbound component INV mapped to black box
@W: CD639 :"syng0a00300":474:9:474:9|Bit <8> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <9> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <10> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <11> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <12> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <13> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <14> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <15> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <16> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <17> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <18> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <19> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <20> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <21> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <22> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <23> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <24> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <25> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <26> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <27> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <28> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <29> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <30> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <31> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <32> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <33> of signal e is undriven 
@W: CD639 :"syng0a00300":474:9:474:9|Bit <34> of signal e is undriven 
@N: CD630 :"syng0a00300":191:7:191:20|Synthesizing work.dwact_tl_l2xor.impl1 
@W: CD280 :"syng0a00300":215:12:215:14|Unbound component OR3 mapped to black box
@W: CD280 :"syng0a00300":223:12:223:16|Unbound component XNOR2 mapped to black box
@N: CD630 :"syng0a00300":223:12:223:16|Synthesizing work.xnor2.syn_black_box 
Post processing for work.xnor2.syn_black_box
@N: CD630 :"syng0a00300":215:12:215:14|Synthesizing work.or3.syn_black_box 
Post processing for work.or3.syn_black_box
Post processing for work.dwact_tl_l2xor.impl1
@N: CD630 :"syng0a00300":155:7:155:18|Synthesizing work.dwact_tl_or3.impl1 
Post processing for work.dwact_tl_or3.impl1
@N: CD630 :"syng0a00300":81:7:81:18|Synthesizing work.dwact_tl_or2.impl1 
@W: CD280 :"syng0a00300":103:10:103:12|Unbound component OR2 mapped to black box
@N: CD630 :"syng0a00300":103:10:103:12|Synthesizing work.or2.syn_black_box 
Post processing for work.or2.syn_black_box
Post processing for work.dwact_tl_or2.impl1
@N: CD630 :"syng0a00300":332:7:332:20|Synthesizing work.dwact_bl_xnor2.impl1 
Post processing for work.dwact_bl_xnor2.impl1
@N: CD630 :"syng0a00300":369:12:369:14|Synthesizing work.inv.syn_black_box 
Post processing for work.inv.syn_black_box
@N: CD630 :"syng0a00300":18:7:18:18|Synthesizing work.dwact_tl_gnd.impl1 
@W: CD280 :"syng0a00300":38:10:38:12|Unbound component GND mapped to black box
@N: CD630 :"syng0a00300":38:10:38:12|Synthesizing work.gnd.syn_black_box 
Post processing for work.gnd.syn_black_box
Post processing for work.dwact_tl_gnd.impl1
Post processing for work.dwact_bl_fincdec.impl1
Post processing for work.dec.fdec
Post processing for work.top.gen